參數(shù)資料
型號(hào): PIC16C71-20/SO
廠商: Microchip Technology
文件頁數(shù): 26/177頁
文件大小: 0K
描述: IC MCU OTP 1KX14 A/D 18SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 42
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 13
程序存儲(chǔ)器容量: 1.75KB(1K x 14)
程序存儲(chǔ)器類型: OTP
RAM 容量: 36 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
包裝: 管件
配用: XLT18SO-1-ND - SOCKET TRANSITION 18SOIC 300MIL
309-1011-ND - ADAPTER 18-SOIC TO 18-DIP
309-1010-ND - ADAPTER 18-SOIC TO 18-DIP
AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
121
7593L–AVR–09/12
AT90USB64/128
15.4
Counter unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 15-2 shows a block diagram of the counter and its surroundings.
Figure 15-2. Counter unit block diagram.
Signal description (internal signals):
Count
Increment or decrement TCNTn by 1.
Direction
Select between increment and decrement.
Clear
Clear TCNTn (set all bits to zero).
clk
Tn
Timer/Counter clock.
TOP
Signalize that TCNTn has reached maximum value.
BOTTOM
Signalize that TCNTn has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) con-
taining the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight
bits. The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNTnH I/O location, the CPU accesses the high byte temporary register (TEMP).
The temporary register is updated with the TCNTnH value when the TCNTnL is read, and
TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNTn Register when the
counter is counting that will give unpredictable results. The special cases are described in the
sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
Tn). The clkTn can be generated from an external or internal clock source,
selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the
timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of
whether clk
Tn is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB).
There are close connections between how the counter behaves (counts) and how waveforms
are generated on the Output Compare outputs OCnx. For more details about advanced counting
sequences and waveform generation, see Section “Modes of operation” on page 127.
TEMP (8-bit)
DATA BUS (8-bit)
TCNTn (16-bit counter)
TCNTnH (8-bit)
TCNTnL (8-bit)
Control logic
Count
Clear
Direction
TOVn
(Int.Req.)
Clock select
TOP
BOTTOM
Tn
Edge
detector
(From prescaler)
clk
Tn
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