參數(shù)資料
型號(hào): PIC16C71-20/SO
廠商: Microchip Technology
文件頁數(shù): 72/177頁
文件大?。?/td> 0K
描述: IC MCU OTP 1KX14 A/D 18SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 42
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 13
程序存儲(chǔ)器容量: 1.75KB(1K x 14)
程序存儲(chǔ)器類型: OTP
RAM 容量: 36 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
包裝: 管件
配用: XLT18SO-1-ND - SOCKET TRANSITION 18SOIC 300MIL
309-1011-ND - ADAPTER 18-SOIC TO 18-DIP
309-1010-ND - ADAPTER 18-SOIC TO 18-DIP
AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
163
7593L–AVR–09/12
AT90USB64/128
a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no
matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin
Description of wake up from Power-save or ADC Noise Reduction mode when the timer is
clocked asynchronously: When the interrupt condition is met, the wake up process is started
on the following cycle of the timer clock, that is, the timer is always advanced by at least one
before the processor can read the counter value. After wake-up, the MCU is halted for four
cycles, it executes the interrupt routine, and resumes execution from the instruction following
SLEEP
Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect
result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be
done through a register synchronized to the internal I/O clock domain. Synchronization takes
place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O
clock (clk
I/O) again becomes active, TCNT2 will read as the previous value (before entering
sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from
Power-save mode is essentially unpredictable, as it depends on the wake-up time. The
recommended procedure for reading TCNT2 is thus as follows:
a.
Write any value to either of the registers OCR2x or TCCR2x.
b.
Wait for the corresponding Update Busy Flag to be cleared.
c.
Read TCNT2.
During asynchronous operation, the synchronization of the Interrupt Flags for the
asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore
advanced by at least one before the processor can read the timer value causing the setting of
the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not
synchronized to the processor clock
16.9.3
TIMSK2 – Timer/Counter2 Interrupt Mask Register
Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable
When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed
if a compare match in Timer/Counter2 occurs, that is, when the OCF2B bit is set in the
Timer/Counter2 Interrupt Flag Register – TIFR2.
Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a compare match in Timer/Counter2 occurs, that is, when the OCF2A bit is set in the
Timer/Counter2 Interrupt Flag Register – TIFR2.
Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, that is, when the TOV2 bit is set in the Timer/Counter2 Inter-
rupt Flag Register – TIFR2.
Bit
7
65
43
2
1
0
––
–OCIE2B
OCIE2A
TOIE2
TIMSK2
Read/write
RR
RR/W
R/W
Initial value
00
0
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