2002 Microchip Technology Inc.
DS41120B-page 11
PIC16C717/770/771
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The special function registers can be classified into two
sets; core (CPU) and peripheral. Those registers asso-
ciated with the core functions are described in detail in
this section. Those related to the operation of the
peripheral features are described in detail in that
peripheral feature section.
TABLE 2-1:
PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Details
on
Page:
Bank 0
00h
(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
23
01h
TMR0
Timer0 module
’
s register
xxxx xxxx
45
02h
(3)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
22
03h
(3)
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
14
04h
(3)
FSR
Indirect data memory address pointer
xxxx xxxx
23
05h
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx 0000
25
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xx11
33
07h
—
Unimplemented
—
—
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
0Ah
(1,3)
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
22
0Bh
(3)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
16
0Ch
PIR1
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
-0---0000
18
0Dh
PIR2
LVDIF
—
—
—
BCLIF
—
—
—
0--- 0---
20
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx
47
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx
47
10h
T1CON
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
--00 0000
47
11h
TMR2
Timer2 module
’
s register
0000 0000
51
12h
T2CON
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
51
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
70
14h
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
67
15h
CCPR1L
Capture/Compare/PWM Register1 (LSB)
xxxx xxxx
54
16h
CCPR1H
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx
54
17h
CCP1CON
PWM1M1
PWM1M0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
0000 0000
53
18h
—
Unimplemented
—
—
19h
—
Unimplemented
—
—
1Ah
—
Unimplemented
—
—
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
1Eh
ADRESH
A/D High Byte Result Register
xxxx xxxx
107
1Fh
ADCON0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
CHS3
ADON
0000 0000
107
Legend:
x
= unknown,
u
= unchanged,
q
= value depends on condition, - = unimplemented read as
’
0
’
.
Shaded locations are unimplemented, read as
‘
0
’
.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
2:
Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3:
These registers can be addressed from any bank.