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2002 Microchip Technology Inc.
DS41120B-page 49
PIC16C717/770/771
6.2
Timer1 Oscillator
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 6-1 shows the capacitor
selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 6-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
6.3
Timer1 Interrupt
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled/disabled by setting/clear-
ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
6.4
Resetting Timer1 using a CCP
Trigger Output
If the ECCP module is configured in Compare mode to
generate a
“
special event trigger" (CCP1M<3:0> =
1011
), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
Timer1 must be configured for either timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from ECCP, the write will take prece-
dence.
In this mode of operation, the CCPR1H:CCPR1L regis-
ters pair effectively becomes the period register for
Timer1.
TABLE 6-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Osc Type
LP
Freq
32 kHz
100 kHz
200 kHz
C1
C2
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
These values are for design guidance only.
Note 1:
Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2:
Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components.
Note:
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
RESETS
0Bh,8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
-0-- 0000
-0-- 0000
8Ch
PIE1
—
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE
-0-- 0000
-0-- 0000
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
10h
T1CON
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
--00 0000
--uu uuuu
Legend:
x = unknown, u = unchanged, - = unimplemented read as
’
0
’
. Shaded cells are not used by the Timer1 module.