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參數(shù)資料
| 型號： | PIC16C74A-04I/P |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 62/114頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 4KX14 A/D PWM 40DIP |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標準包裝： | 10 |
| 系列： | PIC® 16C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 33 |
| 程序存儲器容量： | 7KB（4K x 14） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 192 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x8b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
| 配用： | 444-1001-ND - DEMO BOARD FOR PICMICRO MCU |
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1997 Microchip Technology Inc.
DS30390E-page 51
PIC16C7X
5.5
PORTE and TRISE Register
PORTE has three pins RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually congurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
I/O PORTE becomes control inputs for the micropro-
cessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are congured as digital
inputs) and that register ADCON1 is congured for dig-
ital I/O. In this mode the input buffers are TTL.
Figure 5-9 shows the TRISE register, which also con-
trols the parallel slave port operation.
PORTE pins are multiplexed with analog inputs. The
operation of these pins is selected by control bits in the
ADCON1 register. When selected as an analog input,
these pins will read as '0's.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins congured as inputs when
using them as analog inputs.
Applicable Devices
72 73 73A 74 74A 76 77
FIGURE 5-8:
PORTE BLOCK DIAGRAM (IN
I/O PORT MODE)
Note:
On a Power-on Reset these pins are con-
gured as analog inputs.
Data
bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
Q
D
CK
Q
D
CK
EN
QD
EN
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 5-9:
TRISE REGISTER (ADDRESS 89h)
R-0
R/W-0
U-0
R/W-1
IBF
OBF
IBOV
PSPMODE
—
bit2
bit1
bit0
R
= Readable bit
W = Writable bit
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7
bit0
bit 7 :
IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6:
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5:
IBOV: Input Buffer Overow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overow occurred
bit 4:
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bit 3:
Unimplemented: Read as '0'
PORTE Data Direction Bits
bit 2:
Bit2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1:
Bit1: Direction Control bit for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0:
Bit0: Direction Control bit for pin RE0/RD/AN5
1 = Input
0 = Output
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