參數(shù)資料
型號: PIC16C74A-10/P
廠商: Microchip Technology
文件頁數(shù): 41/114頁
文件大?。?/td> 0K
描述: IC MCU OTP 4KX14 A/D PWM 40DIP
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 10
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 10MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: OTP
RAM 容量: 192 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
配用: 444-1001-ND - DEMO BOARD FOR PICMICRO MCU
PIC16C7X
DS30390E-page 32
1997 Microchip Technology Inc.
4.2.2.3
INTCON REGISTER
The INTCON Register is a readable and writable regis-
ter which contains various enable and ag bits for the
TMR0 register overow, RB Port change and External
RB0/INT pin interrupts.
Applicable Devices
72 73 73A 74 74A 76 77
Note:
Interrupt ag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
FIGURE 4-9:
INTCON REGISTER
(ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
R
= Readable bit
W = Writable bit
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7
bit0
bit 7:
GIE:(1) Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5:
T0IE: TMR0 Overow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 Overow Interrupt Flag bit
1 = TMR0 register has overowed (must be cleared in software)
0 = TMR0 register did not overow
bit 1:
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note 1: For the PIC16C73 and PIC16C74, if an interrupt occurs while the GIE bit is being cleared, the GIE bit
may be unintentionally re-enabled by the RETFIE instruction in the user’s Interrupt Service Routine.
Refer to Section 14.5 for a detailed description.
Interrupt ag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ag bits are clear prior to
enabling an interrupt.
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