參數(shù)資料
型號： PIC16C74A-10/P
廠商： Microchip Technology
文件頁數(shù)： 80/114頁
文件大?。?/td> 0K
描述： IC MCU OTP 4KX14 A/D PWM 40DIP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 10
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 10MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 33
程序存儲器容量： 7KB（4K x 14）
程序存儲器類型： OTP
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
配用： 444-1001-ND - DEMO BOARD FOR PICMICRO MCU
PIC16C7X
DS30390E-page 68
1997 Microchip Technology Inc.
8.5
Resetting Timer1 using a CCP Trigger
Output
The CCP2 module is not implemented on the
PIC16C72 device.
If the CCP1 or CCP2 module is congured in compare
mode
to
generate
a
“special
event
trigger"
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1.
Timer1 must be congured for either timer or synchro-
nized counter mode to take advantage of this feature.
If Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ters pair effectively becomes the period register for
Timer1.
Applicable Devices
72 73 73A 74 74A 76 77
Note:
The special event triggers from the CCP1
and CCP2 modules will not set interrupt
ag bit TMR1IF (PIR1<0>).
8.6
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other reset except by the CCP1 and CCP2
special event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other resets, the register is
unaffected.
8.7
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
Applicable Devices
72 73 73A 74 74A 76 77
Applicable Devices
72 73 73A 74 74A 76 77
TABLE 8-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
PSPIF(1,2) ADIF
RCIF(2)
TXIF(2)
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
8Ch
PIE1
PSPIE(1,2) ADIE
RCIE(2)
TXIE(2)
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0Eh
TMR1L
Holding register for the Least Signicant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
0Fh
TMR1H
Holding register for the Most Signicant Byte of the 16-bit TMR1 register
xxxx xxxx
uuuu uuuu
10h
T1CON
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend:
x
= unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1:
Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.
2:
The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'.
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