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參數(shù)資料
| 型號： | pic16cr54c |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | ROM-Based 8-Bit CMOS Microcontroller Series(8位CMOS微控制器) |
| 中文描述： | 基于ROM的8位CMOS微控制器系列（8位的CMOS微控制器） |
| 文件頁數(shù)： | 30/84頁 |
| 文件大?。?/td> | 654K |
| 代理商： | PIC16CR54C |
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PIC16CR54C
DS40191A-page 30
Preliminary
1998 Microchip Technology Inc.
7.4
Power-On Reset (POR)
The PIC16CR54C incorporates on-chip Power-On
Reset (POR) circuitry which provides an internal chip
reset for most power-up situations. To use this feature,
the user merely ties the MCLR/V
PP
pin to V
DD
. A
simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 7-7.
The Power-On Reset circuit and the Device Reset
Timer (Section 7.5) circuit are closely related. On
power-up, the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR
to be high. After the time-out period, which is typically
18 ms, it will reset the reset latch and thus end the
on-chip reset signal.
A power-up example where MCLR is not tied to V
DD
is
shown in Figure 7-9. V
DD
is allowed to rise and
stabilize before bringing MCLR high. The chip will
actually come out of reset T
DRT
msec after MCLR
goes high.
In Figure 7-10, the on-chip Power-On Reset feature is
being used (MCLR and V
DD
are tied together). The
V
DD
is stable before the start-up timer times out and
there is no problem in getting a proper reset. However,
Figure 7-11 depicts a problem situation where V
DD
rises too slowly. The time between when the DRT
senses a high on the MCLR/V
PP
pin, and when the
MCLR/V
PP
pin (and V
DD
) actually reach their full value,
is too long. In this situation, when the start-up timer
times out, V
DD
has not reached the V
DD
(min) value
and the chip is, therefore, not guaranteed to function
correctly. For such situations, we recommend that
external RC circuits be used to achieve longer POR
delay times (Figure 7-8).
For more information on PIC16CR54C POR, see
Power-Up Considerations- AN522 in the Embedded
Control Handbook.
The POR circuit does not produce an internal reset
when V
DD
declines.
Note:
When the device starts normal operation
(exits the reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be meet to ensure
operation. If these conditions are not met,
the device must be held in reset until the
operating conditions are met.
FIGURE 7-8:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
V
DD
POWER-UP)
V
DD
C
R1
R
D
MCLR
PIC16CR54C
V
DD
External Power-On Reset circuit is required
only if V
DD
power-up is too slow. The diode D
helps discharge the capacitor quickly when
V
DD
powers down.
R < 40 k
is recommended to make sure that
voltage drop across R does not violate the
device electrical specification.
R1 = 100
to 1 k
will limit any current
flowing into MCLR from external capacitor C
in the event of MCLR pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
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