參數(shù)資料
型號: PIC16F707-I/MV
廠商: Microchip Technology
文件頁數(shù): 7/123頁
文件大?。?/td> 0K
描述: MCU PIC 14KB FLASH 40-UQFN
產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
特色產(chǎn)品: Extreme Low Power (XLP) Microcontrollers
標(biāo)準(zhǔn)包裝: 73
系列: PIC® XLP™ mTouch™ 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 14KB(8K x 14)
程序存儲器類型: 閃存
RAM 容量: 363 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 14x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-UFQFN 裸露焊盤
包裝: 管件
PIC18F2331/2431/4331/4431
DS39616D-page 104
2010 Microchip Technology Inc.
REGISTER 10-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
U-0
R/W-0
PTIF
IC3DRIF
IC2QEIF
IC1IF
TMR5IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented:
Read as ‘0’
bit 4
PTIF:
PWM Time Base Interrupt bit
1
= PWM time base matched the value in the PTPER registers. Interrupt is issued according to the
postscaler settings. PTIF must be cleared in software.
0
= PWM time base has not matched the value in the PTPER registers
bit 3
IC3DRIF:
IC3 Interrupt Flag/Direction Change Interrupt Flag bit
IC3 Enabled (CAP3CON<3:0>):
1
= TMR5 value was captured by the active edge on CAP3 input (must be cleared in software)
0
= TMR5 capture has not occurred
QEI Enabled (QEIM<2:0>):
1
= Direction of rotation has changed (must be cleared in software)
0
= Direction of rotation has not changed
bit 2
IC2QEIF:
IC2 Interrupt Flag/QEI Interrupt Flag bit
IC2 Enabled (CAP2CON<3:0>):
1
= TMR5 value was captured by the active edge on CAP2 input (must be cleared in software)
0
= TMR5 capture has not occurred
QEI Enabled (QEIM<2:0>):
1
= The QEI position counter has reached the MAXCNT value, or the index pulse, INDX, has been
detected. Depends on the QEI operating mode enabled. Must be cleared in software.
0
= The QEI position counter has not reached the MAXCNT value or the index pulse has not been
detected
bit 1
IC1 Enabled (CAP1CON<3:0>):
1
= TMR5 value was captured by the active edge on CAP1 input (must be cleared in software)
0
= TMR5 capture has not occurred
QEI Enabled (QEIM<2:0>), Velocity Measurement Mode Enabled (VELM = 0 in QEICON register):
1
= Timer5 value was captured by the active velocity edge (based on PHA or PHB input). CAP1REN
bit must be set in CAP1CON register. IC1IF must be cleared in software.
0
= Timer5 value was not captured by the active velocity edge
bit 0
TMR5IF:
Timer5 Interrupt Flag bit
1
= Timer5 time base matched the PR5 value (must be cleared in software)
0
= Timer5 time base did not match the PR5 value
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