參數(shù)資料
型號: PIC16F785-I/SS
廠商: Microchip Technology
文件頁數(shù): 123/206頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 2KX14 20SSOP
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 67
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 17
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 14x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 639 (CN2011-ZH PDF)
配用: XLT20SS1-1-ND - SOCKET TRANSITION 20DIP 20SSOP
XLT20SS-1-ND - SOCKET TRANSITION 18DIP 20SSOP
AC162060-ND - HEADER INTRFC MPLAB ICD2 20PIN
AC164307-ND - MODULE SKT FOR PM3 28SSOP
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2008 Microchip Technology Inc.
DS41249E-page 21
PIC16F785/HV785
2.3
PCL and PCLATH
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The program counter
is 13 bits wide. The low byte is called the PCL register.
The PCL register is readable and writable. The high
byte of the PC Register is called the PCH register. This
register contains PC<12:8> bits which are not directly
readable or writable. All updates to the PCH register
goes through the PCLATH register.
On any Reset, the PC is cleared. Figure 2-3 shows the
two situations for loading the PC. The upper example
of Figure 2-3 shows how the PC is loaded on a write to
PCL in the PCLATH Register
→ PCH. The lower exam-
ple of Figure 2-3 shows how the PC is loaded during a
CALL
or GOTO instruction in the PCLATH Register
PCH).
2.3.1
MODIFYING PCL
Executing any instruction with the PCL register as the
destination
simultaneously
causes
the
Program
Counter PC<12:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper 5 bits to the PCLATH register.
When the lower 8 bits are written to the PCL register, all
13 bits of the program counter will change to the values
contained in the PCLATH register and those being
written to the PCL register.
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). Care should be
exercised when jumping into a look-up table or
program branch table (computed GOTO) by modifying
the PCL register. Assuming that PCLATH is set to the
table start address, if the table length is greater than
255 instructions or if the lower 8 bits of the memory
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.
For more information refer to Application Note AN556,
“Implementing a Table Read” (DS00556).
2.3.2
PROGRAM MEMORY PAGING
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When using a CALL or GOTO instruction,
the Most Significant bits of the address are provided by
PCLATH<4:3> (page select bits). When using a CALL
or GOTO instruction, the user must ensure that the page
select bits are programmed so that the desired destina-
tion program memory page is addressed. When the
CALL
instruction (or interrupt) is executed, the entire
13-bit PC return address is PUSHed onto the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not required for the RETURN or RETFIE instructions
(which POPs the address from the stack).
FIGURE 2-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.3
STACK
The PIC16F785/HV785 family has an 8-level deep x
13-bit wide hardware stack (see Figure 2-1). The stack
space is not part of either program or data space and
the Stack Pointer is not readable or writable. The PC is
PUSHed onto the stack when a CALL instruction is
executed or an interrupt causes a branch. The stack is
POPed in the event of a RETURN, RETLW or RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
PUSH overwrites the value that was stored from the
first PUSH. The tenth PUSH overwrites the second
PUSH (and so on).
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL,
RETURN,
RETLW
and RETFIE
instructions
or
the
vectoring
to
an
interrupt address.
PC
12
8
7
0
5
PCLATH<4:0>
PCLATH
Instruction with
ALU result
GOTO, CALL
Opcode <10:0>
8
PC
12
11 10
0
11
PCLATH<4:3>
PCH
PCL
87
2
PCLATH
PCH
PCL
PCL as
Destination
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