參數(shù)資料
型號: PIC16F84-04I/SO
廠商: Microchip Technology
文件頁數(shù): 47/80頁
文件大?。?/td> 0K
描述: IC MCU FLASH 1KX14 EE 18SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 42
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 1.75KB(1K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量: 68 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
包裝: 管件
配用: XLT18SO-1-ND - SOCKET TRANSITION 18SOIC 300MIL
309-1075-ND - ADAPTER 18-SOIC TO 18-SOIC
309-1011-ND - ADAPTER 18-SOIC TO 18-DIP
309-1010-ND - ADAPTER 18-SOIC TO 18-DIP
AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
51
M9999-083109-2.0
Bit
Default Value
R/W
Description
1
0x0
RW
RXICMPFCC Receive ICMP Frame Checksum Check Enable
When this bit is set, the KSZ8851SNL will check for correct ICMP checksum for incoming
ICMP frames (only for non-fragment frame). Any received ICMP frames with incorrect
checksum will be discarded.
0
0x0
RW
RXSAF Receive Source Address Filtering
When this bit is set, the KSZ8851SNL will drop the frame if the source address is same as
MAC address in MARL, MARM, MARH registers.
TXQ Memory Information Register (0x78 – 0x79): TXMIR
This register indicates the amount of free memory available in the TXQ of the QMU module.
Bit
Default Value
R/W
Description
15-13
-
RO
Reserved
12-0
-
RO
TXMA Transmit Memory Available
The amount of memory available is represented in units of byte. The TXQ memory is
used for both frame payload, control word.
Note: Software must be written to ensure that there is enough memory for the next
transmit frame including control information before transmit data is written to the TXQ.
0x7A – 0x7B: Reserved
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR
This register indicates the received frame header status information, the received frames are reported in RXFCTR
register. This register contains the status information for the frame received and the CPU can read so many times same
as the frame count value in the RXFCTR.
Bit
Default Value
R/W
Description
15
-
RO
RXFV Receive Frame Valid
When this bit is set, it indicates that the present frame in the receive packet memory is
valid. The status information currently in this location is also valid.
When clear, it indicates that there is either no pending receive frame or that the current
frame is still in the process of receiving.
14
-
RO
Reserved
13
-
RO
RXICMPFCS Receive ICMP Frame Checksum Status
When this bit is set, the KSZ8851SNL received ICMP frame checksum field is incorrect.
12
-
RO
RXIPFCS Receive IP Frame Checksum Status
When this bit is set, the KSZ8851SNL received IP header checksum field is incorrect.
11
-
RO
RXTCPFCS Receive TCP Frame Checksum Status
When this bit is set, the KSZ8851SNL received TCP frame checksum field is incorrect.
10
-
RO
RXUDPFCS Receive UDP Frame Checksum Status
When this bit is set, the KSZ8851SNL received UDP frame checksum field is incorrect.
9-8
-
RO
Reserved
7
-
RO
RXBF Receive Broadcast Frame
When this bit is set, it indicates that this frame has a broadcast address.
6
-
RO
RXMF Receive Multicast Frame
When this bit is set, it indicates that this frame has a multicast address (including the
broadcast address).
5
-
RO
RXUF Receive Unicast Frame
When this bit is set, it indicates that this frame has a unicast address.
4
-
RO
RXMR Receive MII Error
When set, it indicates that there is an MII symbol error on the received frame.
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