參數(shù)資料
型號: PIC16LF74-I/PTG
廠商: Microchip Technology
文件頁數(shù): 65/104頁
文件大?。?/td> 0K
描述: IC MCU FLASH 4KX14 44TQFP
標(biāo)準(zhǔn)包裝: 160
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: 閃存
RAM 容量: 192 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
Micrel, Inc.
KSZ8851-16MLLJ
March 2010
55
M9999-030210-1.0
Transmit Control Register (0x70 – 0x71): TXCR
This register holds control information programmed by the CPU to control the QMU transmit module function.
Bit
Default Value
R/W
Description
15-9
-
RO
Reserved.
8
0x0
RW
TCGICMP Transmit Checksum Generation for ICMP
When this bit is set, The KSZ8851-16MLLJ is enabled to transmit ICMP frame (only for
non-fragment frame) checksum generation.
7
0x0
RO
Reserved.
6
0x0
RW
TCGTCP Transmit Checksum Generation for TCP
When this bit is set, The KSZ8851-16MLLJ is enabled to transmit TCP frame
checksum generation.
5
0x0
RW
TCGIP Transmit Checksum Generation for IP
When this bit is set, The KSZ8851-16MLLJ is enabled to transmit IP header checksum
generation.
4
0x0
RW
FTXQ Flush Transmit Queue
When this bit is set, The transmit queue memory is cleared and TX frame pointer is
reset.
Note: Disable the TXE transmit enable bit[0] first before set this bit, then clear this bit
to normal operation.
3
0x0
RW
TXFCE Transmit Flow Control Enable
When this bit is set and the KSZ8851-16MLLJ is in full-duplex mode, flow control is
enabled. The KSZ8851-16MLLJ transmits a PAUSE frame when the Receive Buffer
capacity reaches a threshold level that will cause the buffer to overflow.
When this bit is set and the KSZ8851-16MLLJ is in half-duplex mode, back-pressure
flow control is enabled. When this bit is cleared, no transmit flow control is enabled.
2
0x0
RW
TXPE Transmit Padding Enable
When this bit is set, the KSZ8851-16MLLJ automatically adds a padding field to a
packet shorter than 64 bytes.
Note: Setting this bit requires enabling the add CRC feature (bit1=1) to avoid CRC
errors for the transmit packet.
1
0x0
RW
TXCE Transmit CRC Enable
When this bit is set, the KSZ8851-16MLLJ automatically adds a 32-bit CRC checksum
field to the end of a transmit frame.
0
0x0
RW
TXE Transmit Enable
When this bit is set, the transmit module is enabled and placed in a running state.
When reset, the transmit process is placed in the stopped state after the transmission
of the current frame is completed.
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