參數(shù)資料
型號: PIC17C766T-33I/PT
廠商: Microchip Technology
文件頁數(shù): 53/159頁
文件大?。?/td> 0K
描述: IC MCU OTP 16KX16 A/D 80TQFP
標(biāo)準(zhǔn)包裝: 1,200
系列: PIC® 17C
核心處理器: PIC
芯體尺寸: 8-位
速度: 33MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 66
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: OTP
RAM 容量: 902 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-TQFP
包裝: 帶卷 (TR)
配用: XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
AC174011-ND - MODULE SKT PROMATEII 80TQFP
216
8006K–AVR–10/10
ATtiny24/44/84
ROR
Rd
Rotate Right Through Carry
Rd(7)
←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n)
← Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)
←Rd(7..4),Rd(7..4)←Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s)
← 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s)
← 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T
← Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b)
← TNone
1
SEC
Set Carry
C
← 1C
1
CLC
Clear Carry
C
← 0
C
1
SEN
Set Negative Flag
N
← 1N
1
CLN
Clear Negative Flag
N
← 0
N
1
SEZ
Set Zero Flag
Z
← 1Z
1
CLZ
Clear Zero Flag
Z
← 0
Z
1
SEI
Global Interrupt Enable
I
← 1I
1
CLI
Global Interrupt Disable
I
← 0
I
1
SES
Set Signed Test Flag
S
← 1S
1
CLS
Clear Signed Test Flag
S
← 0
S
1
SEV
Set Twos Complement Overflow.
V
← 1V
1
CLV
Clear Twos Complement Overflow
V
← 0
V
1
SET
Set T in SREG
T
← 1T
1
CLT
Clear T in SREG
T
← 0
T
1
SEH
Set Half Carry Flag in SREG
H
← 1H
1
CLH
Clear Half Carry Flag in SREG
H
← 0
H
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
Rd
← Rr
None
1
MOVW
Rd, Rr
Copy Register Word
Rd+1:Rd
← Rr+1:Rr
None
1
LDI
Rd, K
Load Immediate
Rd
← KNone
1
LD
Rd, X
Load Indirect
Rd
← (X)
None
2
LD
Rd, X+
Load Indirect and Post-Inc.
Rd
← (X), X ← X + 1
None
2
LD
Rd, - X
Load Indirect and Pre-Dec.
X
← X - 1, Rd ← (X)
None
2
LD
Rd, Y
Load Indirect
Rd
← (Y)
None
2
LD
Rd, Y+
Load Indirect and Post-Inc.
Rd
← (Y), Y ← Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Dec.
Y
← Y - 1, Rd ← (Y)
None
2
LDD
Rd,Y+q
Load Indirect with Displacement
Rd
← (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd
← (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-Inc.
Rd
← (Z), Z ← Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Dec.
Z
← Z - 1, Rd ← (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd
← (Z + q)
None
2
LDS
Rd, k
Load Direct from SRAM
Rd
← (k)
None
2
ST
X, Rr
Store Indirect
(X)
← Rr
None
2
ST
X+, Rr
Store Indirect and Post-Inc.
(X)
← Rr, X ← X + 1
None
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X
← X - 1, (X) ← Rr
None
2
ST
Y, Rr
Store Indirect
(Y)
← Rr
None
2
ST
Y+, Rr
Store Indirect and Post-Inc.
(Y)
← Rr, Y ← Y + 1
None
2
ST
- Y, Rr
Store Indirect and Pre-Dec.
Y
← Y - 1, (Y) ← Rr
None
2
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q)
← Rr
None
2
ST
Z, Rr
Store Indirect
(Z)
← Rr
None
2
ST
Z+, Rr
Store Indirect and Post-Inc.
(Z)
← Rr, Z ← Z + 1
None
2
ST
-Z, Rr
Store Indirect and Pre-Dec.
Z
← Z - 1, (Z) ← Rr
None
2
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q)
← Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k)
← Rr
None
2
LPM
Load Program Memory
R0
← (Z)
None
3
LPM
Rd, Z
Load Program Memory
Rd
← (Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Inc
Rd
← (Z), Z ← Z+1
None
3
SPM
Store Program Memory
(z)
← R1:R0
None
IN
Rd, P
In Port
Rd
← PNone
1
OUT
P, Rr
Out Port
P
← Rr
None
1
PUSH
Rr
Push Register on Stack
STACK
← Rr
None
2
POP
Rd
Pop Register from Stack
Rd
← STACK
None
2
MCU CONTROL INSTRUCTIONS
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
Watchdog Reset
(see specific descr. for WDR/Timer)
None
1
BREAK
Break
For On-chip Debug Only
None
N/A
Mnemonics
Operands
Description
Operation
Flags
#Clocks
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