參數(shù)資料
型號: PIC18F25K20-I/ML
廠商: Microchip Technology
文件頁數(shù): 2/42頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 16KX16 28QFN
產(chǎn)品培訓(xùn)模塊: PIC18 K-Series
XLP Deep Sleep Mode
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 61
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 64MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 24
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 1.5K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 656 (CN2011-ZH PDF)
配用: AC164112-ND - VOLTAGE LIMITER MPLAB ICD2 VPP
AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
PIC18F2XK20/4XK20
DS41297F-page 10
Advance Information
2009 Microchip Technology Inc.
2.4
High-Level Overview of the
Programming Process
Figure 2-11 shows the high-level overview of the
programming process. First, a Bulk Erase is performed.
Next, the code memory, ID locations and data
EEPROM are programmed. These memories are then
verified to ensure that programming was successful. If
no errors are detected, the Configuration bits are then
programmed and verified.
FIGURE 2-11:
HIGH-LEVEL
PROGRAMMING FLOW
2.5
Entering and Exiting High-Voltage
ICSP Program/Verify Mode
As shown in Figure 2-12, the High-Voltage ICSP
Program/Verify mode is entered by holding PGC and
PGD low and then raising MCLR/VPP/RE3 to VIHH
(high voltage). Once in this mode, the code memory,
data EEPROM, ID locations and Configuration bits can
be accessed and programmed in serial fashion.
Figure 2-13 shows the exit sequence.
The sequence that enters the device into the Program/
Verify mode places all unused I/Os in the high-impedance
state.
FIGURE 2-12:
ENTERING HIGH-VOLTAGE
PROGRAM/VERIFY MODE
FIGURE 2-13:
EXITING HIGH-VOLTAGE
PROGRAM/VERIFY MODE
Start
Program Memory
Program IDs
Program Data EE
Verify Program
Verify IDs
Verify Data
Program
Configuration Bits
Verify
Configuration Bits
Done
Perform Bulk
Erase
MCLR/VPP/RE3
P12
PGD
PGD = Input
PGC
VDD
D110
P13
P1
MCLR/VPP/RE3
P16
PGD
PGD = Input
PGC
VDD
D110
P17
P1
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