參數(shù)資料
型號： PIC18F448-I/PT
廠商： Microchip Technology
文件頁數(shù)： 35/116頁
文件大小： 0K
描述： IC PIC MCU FLASH 8KX16 44TQFP
產(chǎn)品培訓模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝： 160
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 40MHz
連通性： CAN，I²C，SPI，UART/USART
外圍設備： 欠壓檢測/復位，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 33
程序存儲器容量： 16KB（8K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 4.2 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 8x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
配用： XLT44PT3-ND - SOCKET TRAN ICE 44MQFP/TQFP
AC164305-ND - MODULE SKT FOR PM3 44TQFP
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
AC164020-ND - MODULE SKT PROMATEII 44TQFP
PIC16F193X/LF193X
DS41364D-page 286
Preliminary
2009 Microchip Technology Inc.
REGISTER 23-3:
SSPCON2: SSP CONTROL REGISTER 2
R/W-0/0
R-0/0
R/W-0/0
R/S/HS-0/0 R/S/HS-0/0
R/S/HS-0/0
R/W/HS-0/0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Cleared by hardware
S = User set
bit 7
GCEN:
General Call Enable bit (in I2C Slave mode only)
1
= Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0
= General call address disabled
bit 6
ACKSTAT:
Acknowledge Status bit (in I2C mode only)
1
= Acknowledge was not received
0
= Acknowledge was received
bit 5
ACKDT:
Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1
= Not Acknowledge
0
= Acknowledge
bit 4
ACKEN:
Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1
= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0
= Acknowledge sequence idle
bit 3
RCEN:
Receive Enable bit (in I2C Master mode only)
1
= Enables Receive mode for I2C
0
= Receive idle
bit 2
PEN:
Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1
= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0
= Stop condition Idle
bit 1
RSEN:
Repeated Start Condition Enabled bit (in I2C Master mode only)
1
= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0
= Repeated Start condition Idle
bit 0
SEN:
Start Condition Enabled bit (in I2C Master mode only)
In Master mode:
1
= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0
= Start condition Idle
In Slave mode:
1
= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0
= Clock stretching is disabled
Note 1:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
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