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2007 Microchip Technology Inc.
Preliminary
DS39755B-page 379
PIC18F2423/2523/4423/4523
DC Characteristics ...........................................................337
Power-Down and Supply Current ............................328
Supply Voltage .........................................................327
DCFSNZ ..........................................................................291
DECF ...............................................................................290
DECFSZ ...........................................................................291
Development Support ......................................................321
Device Differences ...........................................................373
Device Overview ..................................................................7
Details on Individual Family Members .........................8
Features (table) ............................................................9
New Core Features ......................................................7
Other Special Features ................................................8
Device Reset Timers ..........................................................45
Oscillator Start-up Timer (OST) .................................45
PLL Lock Time-out .....................................................45
Power-up Timer (PWRT) ...........................................45
Time-out Sequence ....................................................45
Direct Addressing ...............................................................69
E
Effect on Standard PIC MCU Instructions ........................318
Effects of Power-Managed Modes on
Various Clock Sources ...............................................31
Electrical Characteristics ..................................................325
Enhanced Capture/Compare/PWM (ECCP) ....................147
Associated Registers ...............................................160
Capture and Compare Modes ..................................148
Capture Mode.
See
Capture (ECCP Module).
Enhanced PWM Mode .............................................149
Outputs and Configuration .......................................148
Pin Configurations for ECCP1 .................................148
PWM Mode.
See
PWM (ECCP Module).
Special Event Trigger ...............................................148
Standard PWM Mode ...............................................148
Timer Resources ......................................................148
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART).
See
EUSART.
Equations
A/D Acquisition Time ................................................232
A/D Minimum Charging Time ...................................232
Errata ...................................................................................6
EUSART
Asynchronous Mode ................................................215
Associated Registers, Receive ........................218
Associated Registers, Transmit .......................216
Auto-Wake-up on Sync
Break Character .......................................218
Break Character Sequence .............................220
Receiver ...........................................................217
Receiving a Break Character ...........................220
Setting Up 9-Bit Mode with
Address Detect ........................................217
Transmitter .......................................................215
Baud Rate Generator
Operation in Power-Managed Mode ................209
Baud Rate Generator (BRG) ....................................209
Associated Registers .......................................210
Auto-Baud Rate Detect ....................................213
Baud Rate Error, Calculating ...........................210
Baud Rates, Asynchronous Modes .................211
High Baud Rate Select (BRGH Bit) .................209
Sampling ..........................................................209
Synchronous Master Mode ...................................... 221
Associated Registers, Receive ........................ 223
Associated Registers, Transmit ....................... 222
Reception ........................................................ 223
Transmission ................................................... 221
Synchronous Slave Mode ........................................ 224
Associated Registers, Receive ........................ 225
Associated Registers, Transmit ....................... 224
Reception ........................................................ 225
Transmission ................................................... 224
Extended Instruction Set
ADDFSR .................................................................. 314
ADDULNK ............................................................... 314
CALLW .................................................................... 315
Considerations for Use ............................................ 318
MOVSF .................................................................... 315
MOVSS .................................................................... 316
PUSHL ..................................................................... 316
SUBFSR .................................................................. 317
SUBULNK ................................................................ 317
Syntax ...................................................................... 313
Using MPLAB IDE Tools ......................................... 320
External Clock Input ........................................................... 24
F
Fail-Safe Clock Monitor ........................................... 253, 265
Exiting Operation ..................................................... 265
Interrupts in Power-Managed Modes ...................... 266
POR or Wake from Sleep ........................................ 266
WDT During Oscillator Failure ................................. 265
Fast Register Stack ........................................................... 56
Flash Program Memory ..................................................... 73
Associated Registers ................................................. 82
Control Registers ....................................................... 74
EECON1 and EECON2 ..................................... 74
TABLAT (Table Latch) Register ........................ 76
TBLPTR (Table Pointer) Register ...................... 76
Erase Sequence ........................................................ 78
Erasing ...................................................................... 78
Operation During Code-Protect ................................. 81
Reading ..................................................................... 77
Table Pointer
Boundaries Based on Operation ....................... 76
Table Pointer Boundaries .......................................... 76
Table Reads and Table Writes .................................. 73
Write Sequence ......................................................... 79
Writing To .................................................................. 79
Protection Against Spurious Writes ................... 81
Unexpected Termination ................................... 81
Write Verify ........................................................ 81
FSCM.
See
Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 292
H
Hardware Multiplier ............................................................ 89
Introduction ................................................................ 89
Operation ................................................................... 89
Performance Comparison .......................................... 89