參數(shù)資料
    型號： PIC18F458-I/L
    廠商： Microchip Technology
    文件頁數(shù)： 82/116頁
    文件大?。?/td> 0K
    描述： IC MCU FLASH 16KX16 CAN 44PLCC
    產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
    8-bit PIC® Microcontroller Portfolio
    標(biāo)準(zhǔn)包裝： 27
    系列： PIC® 18F
    核心處理器： PIC
    芯體尺寸： 8-位
    速度： 40MHz
    連通性： CAN，I²C，SPI，UART/USART
    外圍設(shè)備： 欠壓檢測/復(fù)位，LVD，POR，PWM，WDT
    輸入/輸出數(shù)： 33
    程序存儲器容量： 32KB（16K x 16）
    程序存儲器類型： 閃存
    EEPROM 大?。?/td> 256 x 8
    RAM 容量： 1.5K x 8
    電壓 - 電源 (Vcc/Vdd)： 4.2 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
    振蕩器型： 外部
    工作溫度： -40°C ~ 85°C
    封裝/外殼： 44-LCC（J 形引線）
    包裝： 管件
    配用： AC164309-ND - MODULE SKT FOR PM3 44PLCC
    444-1001-ND - DEMO BOARD FOR PICMICRO MCU
    其它名稱： PIC18F458I/L
    PIC18FXX8
    DS41159E-page 66
    2006 Microchip Technology Inc.
    FIGURE 6-2:
    TABLE WRITE OPERATION
    6.2
    Control Registers
    Several control registers are used in conjunction with
    the TBLRD and TBLWT instructions. These include the:
    EECON1 register
    EECON2 register
    TABLAT register
    TBLPTR registers
    6.2.1
    EECON1 AND EECON2 REGISTERS
    EECON1 is the control register for memory accesses.
    EECON2 is not a physical register. Reading EECON2
    will read all ‘0’s. The EECON2 register is used
    exclusively in the memory write and erase sequences.
    Control bit EEPGD determines if the access will be a
    program or data EEPROM memory access. When
    clear, any subsequent operations will operate on the
    data EEPROM memory. When set, any subsequent
    operations will operate on the program memory.
    Control bit CFGS determines if the access will be to the
    Configuration/Calibration
    registers
    or
    to
    program
    memory/data
    EEPROM
    memory.
    When
    set,
    subsequent operations will operate on Configuration
    registers regardless of EEPGD (see Section 24.0
    selection access is determined by EEPGD.
    The FREE bit, when set, will allow a program memory
    erase operation. When the FREE bit is set, the erase
    operation is initiated on the next WR command. When
    FREE is clear, only writes are enabled.
    The WREN bit, when set, will allow a write operation.
    On power-up, the WREN bit is clear. The WRERR bit is
    set when a write operation is interrupted by a MCLR
    Reset or a WDT Time-out Reset during normal opera-
    tion. In these situations, the user can check the
    WRERR bit and rewrite the location. It is necessary to
    reload the data and address registers (EEDATA and
    EEADR) due to Reset values of zero.
    Control bits, RD and WR, initiate read and write opera-
    tions, respectively. These bits cannot be cleared, only
    set, in software. They are cleared in hardware at the
    completion of the read or write operation. The inability
    to clear the WR bit in software prevents the accidental
    or premature termination of a write operation. The RD
    bit cannot be set when accessing program memory
    (EEPGD = 1).
    Table Pointer(1)
    Table Latch (8-bit)
    TBLPTRH
    TBLPTRL
    TABLAT
    Program Memory
    (TBLPTR)
    TBLPTRU
    Instruction: TBLWT*
    Note
    1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>.
    The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash
    Holding Registers
    Program Memory
    Note:
    Interrupt flag bit, EEIF in the PIR2 register,
    is set when write is complete. It must be
    cleared in software.
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