參數(shù)資料
型號(hào): PIC18F458-I/L
廠商: Microchip Technology
文件頁數(shù): 90/116頁
文件大?。?/td> 0K
描述: IC MCU FLASH 16KX16 CAN 44PLCC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 27
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 1.5K x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
配用: AC164309-ND - MODULE SKT FOR PM3 44PLCC
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
其它名稱: PIC18F458I/L
2006 Microchip Technology Inc.
DS41159E-page 73
PIC18FXX8
EXAMPLE 6-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
6.5.2
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed.The WRERR bit is set when a write
operation is interrupted by a MCLR Reset or a WDT
Time-out Reset during normal operation. In these
situations, users can check the WRERR bit and rewrite
the location.
6.5.4
PROTECTION AGAINST SPURIOUS
WRITES
To reduce the probability against spurious writes to
Flash program memory, the write initiate sequence
must also be followed. See Section 24.0 “Special
Features of the CPU” for more detail.
6.6
Flash Program Operation During
Code Protection
details on code protection of Flash program memory.
WRITE_WORD_TO_HREGS
MOVFW
POSTINC0, W
; get low byte of buffer data
MOVWF
TABLAT
; present data to table latch
TBLWT+*
; write data, perform a short write
; to internal TBLWT holding register.
DECFSZ
COUNTER
; loop until buffers are full
BRA
WRITE_WORD_TO_HREGS
PROGRAM_MEMORY
BSF
EECON1, EEPGD
; point to FLASH program memory
BCF
EECON1, CFGS
; access FLASH program memory
BSF
EECON1, WREN
; enable write to memory
BCF
INTCON, GIE
; disable interrupts
MOVLW
55h
; write 55h
Required
MOVWF
EECON2
Sequence
MOVLW
0AAh
; write 0AAh
MOVWF
EECON2
; start program (CPU stall)
BSF
EECON1, WR
NOP
BSF
INTCON, GIE
; re-enable interrupts
DECFSZ
COUNTER_HI
; loop until done
BRA
PROGRAM_LOOP
BCF
EECON1, WREN
; disable write to memory
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