
2007 Microchip Technology Inc.
Preliminary
DS39682C-page 349
PIC18F45J10 FAMILY
SSPxCON1 (MSSPx Control 1, I
2
C Mode)...............157
SSPxCON1 (MSSPx Control 1, SPI Mode)..............147
SSPxCON2 (MSSPx Control 2, I
2
C Mode)...............158
SSPxSTAT (MSSPx Status, I
2
C Mode)....................156
SSPxSTAT (MSSPx Status, SPI Mode) ...................146
STATUS......................................................................60
STKPTR (Stack Pointer).............................................49
T0CON (Timer0 Control)...........................................111
T1CON (Timer1 Control)...........................................115
T2CON (Timer2 Control)...........................................121
TRISE (PORTE/PSP Control)...................................107
TXSTA (Transmit Status and Control)......................188
WDTCON (Watchdog Timer Control) .......................235
RESET..............................................................................271
Reset...................................................................................37
MCLR Reset, During Power-Managed Modes............37
MCLR Reset, Normal Operation.................................37
Power-on Reset (POR)...............................................37
Programmable Brown-out Reset (BOR) .....................37
Reset Instruction.........................................................37
Stack Full Reset..........................................................37
Stack Underflow Reset ...............................................37
Watchdog Timer (WDT) Reset....................................37
Resets...............................................................................229
Brown-out Reset (BOR)............................................229
Oscillator Start-up Timer (OST) ................................229
Power-on Reset (POR).............................................229
Power-up Timer (PWRT) ..........................................229
RETFIE .............................................................................272
RETLW .............................................................................272
RETURN...........................................................................273
Return Address Stack.........................................................48
Return Stack Pointer (STKPTR) .........................................49
Revision History................................................................341
RLCF.................................................................................273
RLNCF..............................................................................274
RRCF................................................................................274
RRNCF .............................................................................275
S
SCKx.................................................................................145
SDIx ..................................................................................145
SDOx ................................................................................145
SEC_IDLE Mode.................................................................35
SEC_RUN Mode.................................................................32
Serial Clock, SCKx............................................................145
Serial Data In (SDIx).........................................................145
Serial Data Out (SDOx) ....................................................145
Serial Peripheral Interface.
See
SPI Mode.
SETF.................................................................................275
Slave Select (SSx)............................................................145
SLEEP ..............................................................................276
Sleep
OSC1 and OSC2 Pin States.......................................29
Software Simulator (MPLAB SIM).....................................292
Special Event Trigger.
See
Compare (ECCP Module).
Special Event Trigger.
See
Compare (ECCP/CCP Modules).
Special Features of the CPU ............................................229
Special Function Registers .................................................56
Map.............................................................................56
SPI Mode (MSSP)
Associated Registers................................................154
Bus Mode Compatibility............................................153
Clock Speed and Module Interactions......................153
Effects of a Reset......................................................153
Enabling SPI I/O .......................................................149
Master Mode............................................................. 150
Master/Slave Connection ......................................... 149
Operation.................................................................. 148
Operation in Power-Managed Modes....................... 153
Serial Clock .............................................................. 145
Serial Data In............................................................ 145
Serial Data Out......................................................... 145
Slave Mode............................................................... 151
Slave Select.............................................................. 145
Slave Select Synchronization................................... 151
SPI Clock.................................................................. 150
Typical Connection................................................... 149
SSPOV ............................................................................. 176
SSPOV Status Flag.......................................................... 176
SSPxSTAT Register
R/W Bit ............................................................. 159, 160
SSx................................................................................... 145
Stack Full/Underflow Resets............................................... 50
SUBFSR........................................................................... 287
SUBFWB .......................................................................... 276
SUBLW............................................................................. 277
SUBULNK......................................................................... 287
SUBWF............................................................................. 277
SUBWFB .......................................................................... 278
SWAPF............................................................................. 278
T
Table Pointer Operations (table)......................................... 70
Table Reads/Table Writes.................................................. 50
TBLRD.............................................................................. 279
TBLWT ............................................................................. 280
Timer0 .............................................................................. 111
Associated Registers................................................ 113
Clock Source Select (T0CS Bit) ............................... 112
Operation.................................................................. 112
Overflow Interrupt..................................................... 113
Prescaler .................................................................. 113
Prescaler Assignment (PSA Bit)............................... 113
Prescaler Select (T0PS2:T0PS0 Bits)...................... 113
Prescaler.
See
Prescaler, Timer0.
Reads and Writes in 16-Bit Mode............................. 112
Source Edge Select (T0SE Bit) ................................ 112
Switching Prescaler Assignment .............................. 113
Timer1 .............................................................................. 115
16-Bit Read/Write Mode ........................................... 117
Associated Registers................................................ 119
Interrupt .................................................................... 118
Operation.................................................................. 116
Oscillator........................................................... 115, 117
Layout Considerations...................................... 118
Oscillator, as Secondary Clock................................... 26
Overflow Interrupt..................................................... 115
Resetting, Using the ECCP/CCP Special Event
Trigger.............................................................. 118
Special Event Trigger (ECCP).................................. 132
TMR1H Register....................................................... 115
TMR1L Register ....................................................... 115
Use as a Clock Source............................................. 117
Use as a Real-Time Clock........................................ 118
Timer2 .............................................................................. 121
Associated Registers................................................ 122
Interrupt .................................................................... 122
Operation.................................................................. 121
Output....................................................................... 122
PR2 Register.................................................... 128, 133
TMR2-to-PR2 Match Interrupt .......................... 128, 133