參數(shù)資料
型號: PIC18F45J10T-E/PT
廠商: Microchip Technology
文件頁數(shù): 61/80頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 16KX16 44TQFP
標準包裝: 1,200
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 44-TQFP
包裝: 帶卷 (TR)
配用: AC162074-ND - HEADER INTRFC MPLAB ICD2 44TQFP
MA180013-ND - MODULE PLUG-IN 18F45J10 44TQFP
AC162067-ND - HEADER INTRFC MPLAB ICD2 40/28P
AC164330-ND - MODULE SKT FOR 44TQFP 18F45J10
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
64
M9999-083109-2.0
PHY 1 PHY ID Low Register (0xE8 – 0xE9): PHY1ILR
This register contains the PHY ID (low) for the chip.
Bit
Default
R/W
Description
15-0
0x1430
RO
PHYID Low
Low order PHYID bits.
PHY 1 PHY ID High Register (0xEA – 0xEB): PHY1IHR
This register contains the PHY ID (high) for the chip.
Bit
Default
R/W
Description
15-0
0x0022
RO
PHYID High
High order PHYID bits.
PHY 1 Auto-Negotiation Advertisement Register (0xEC – 0xED): P1ANAR
This register contains the auto-negotiation advertisement for the PHY function.
Bit
Default
R/W
Description
Bit is same as:
15
0
RO
Next page
Not supported.
14
0
RO
Reserved
13
0
RO
Remote fault
Not supported.
12-11
0x0
RO
Reserved
10
1
RW
Pause (flow control capability)
1 = advertise pause capability.
0 = do not advertise pause capability.
Bit 4 in P1CR
9
0
RW
Reserved.
8
1
RW
Adv 100 Full
1 = advertise 100 full-duplex capability.
0 = do not advertise 100 full-duplex capability
Bit 3 in P1CR
7
1
RW
Adv 100 Half
1= advertise 100 half-duplex capability.
0 = do not advertise 100 half-duplex capability.
Bit 2 in P1CR
6
1
RW
Adv 10 Full
1 = advertise 10 full-duplex capability.
0 = do not advertise 10 full-duplex capability.
Bit 1 in P1CR
5
1
RW
Adv 10 Half
1 = advertise 10 half-duplex capability.
0 = do not advertise 10 half-duplex capability.
Bit 0 in P1CR
4-0
0x01
RO
Selector Field
802.3
PHY 1 Auto-Negotiation Link Partner Ability Register (0xEE – 0xEF): P1ANLPR
This register contains the auto-negotiation link partner ability for the chip function.
Bit
Default
R/W
Description
Bit is same as:
15
0
RO
Next page
Not supported.
14
0
RO
LP ACK
Not supported.
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