PIC18F6X2X/8X2X
DS39612A-page 350
Advance Information
2003 Microchip Technology Inc.
FIGURE 27-17:
EXAMPLE SPI SLAVE MODE TIMING (CKE =
1
)
82
TABLE 27-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE =
1
)
Param.
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH,
TssL2scL
TscH
SS
↓
to SCK
↓
or SCK
↑
input
T
CY
—
ns
71
71A
72
72A
73A
74
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 T
CY
+ 30
40
1.25 T
CY
+ 30
40
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
(Note 1)
TscL
SCK input low time
(Slave mode)
(Note 1)
(Note 2)
T
B
2
B
TscH2diL,
TscL2diL
TdoR
Last clock edge of Byte 1 to the first clock edge of Byte 2 1.5 T
CY
+ 40
Hold time of SDI data input to SCK edge
100
75
SDO data output rise time
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
—
25
45
25
50
25
45
25
50
100
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
76
77
78
TdoF
TssH2doZ
TscR
SDO data output fall time
SS
↑
to SDO output hi-impedance
SCK output rise time
(Master mode)
—
10
—
—
—
—
—
—
—
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
79
80
TscF
TscH2doV,
TscL2doV
SCK output fall time (Master mode)
SDO data output valid after SCK
edge
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
82
TssL2doV
SDO data output valid after SS
↓
edge
SS
↑
after SCK edge
83
TscH2ssH,
TscL2ssH
1.5 T
CY
+ 40
Note 1:
Requires the use of Parameter #73A.
2:
Only if Parameter #71A and #72A are used.
SS
SCK
(CKP =
0
)
SCK
(CKP =
1
)
SDO
SDI
70
71
72
74
75, 76
MSb
bit 6 - - - - - -1
LSb
77
MSb In
bit 6 - - - -1
LSb In
80
83
Note:
Refer to Figure 27-4 for load conditions.
