參數(shù)資料
型號： PIC18LF2450T-I/SO
廠商： Microchip Technology
文件頁數(shù)： 31/143頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 8KX16 28SOIC
標準包裝： 1,600
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 48MHz
連通性： UART/USART，USB
外圍設備： 欠壓檢測/復位，HLVD，POR，PWM，WDT
輸入/輸出數(shù)： 23
程序存儲器容量： 16KB（8K x 16）
程序存儲器類型： 閃存
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 10x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 帶卷 (TR)
PIC18F2450/4450
DS39760A-page 124
Advance Information
2006 Microchip Technology Inc.
13.1
CCP Module Configuration
The Capture/Compare/PWM module is associated with
a control register (generically, CCP1CON) and a data
register (CCPR1). The data register, in turn, is
comprised of two 8-bit registers: CCPR1L (low byte)
and CCPR1H (high byte). All registers are both
readable and writable.
13.1.1
CCP MODULE AND TIMER
RESOURCES
The CCP module utilizes Timer1 or Timer2, depending
on the mode selected. Timer1 is available to the mod-
ule in Capture or Compare modes, while Timer2 is
available for modules in PWM mode.
TABLE 13-1:
CCP MODE – TIMER
RESOURCE
In Timer1 in Asynchronous Counter mode, the capture
operation will not work.
13.2
Capture Mode
In Capture mode, the CCPR1H:CCPR1L register pair
captures the 16-bit value of the TMR1 register when an
event occurs on the corresponding CCP1 pin. An event
is defined as one of the following:
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
The event is selected by the mode select bits,
CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture
is made, the interrupt request flag bit, CCP1IF, is set; it
must be cleared in software. If another capture occurs
before the value in register CCPR1 is read, the old
captured value is overwritten by the new captured value.
13.2.1
CCP1 PIN CONFIGURATION
In Capture mode, the CCP1 pin should be configured
as an input by setting the corresponding TRIS direction
bit.
13.2.2
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE interrupt enable bit clear to avoid false
interrupts. The interrupt flag bit, CCP1IF, should also
be cleared following any such change in operating
mode.
13.2.3
CCP PRESCALER
There are four prescaler settings in Capture mode.
They are specified as part of the operating mode
selected by the mode select bits (CCP1M3:CCP1M0).
Whenever the CCP module is turned off or Capture
mode is disabled, the prescaler counter is cleared. This
means that any Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a
non-zero
prescaler.
shows
the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 13-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
(CCP1 SHOWN)
FIGURE 13-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer2
Note:
If RC2/CCP1 is configured as an output, a
write to the port can cause a capture
condition.
CLRF
CCP1CON
; Turn CCP module off
MOVLW
NEW_CAPT_PS
; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF
CCP1CON
; Load CCP1CON with
; this value
CCPR1H
CCPR1L
TMR1H
TMR1L
Set CCP1IF
Q1:Q4
CCP1CON<3:0>
CCP1 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
TMR1
Enable
4
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