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參數(shù)資料
| 型號： | PIC18LF258-I/SO |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 33/116頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU CAN FLASH 16K LP 28-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | PIC® 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | CAN，I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 22 |
| 程序存儲器容量： | 32KB（16K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 256 x 8 |
| RAM 容量： | 1.5K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 5x10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 管件 |
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PIC16F193X/LF193X
DS41364D-page 284
Preliminary
2009 Microchip Technology Inc.
REGISTER 23-1:
SSPSTAT: SSP STATUS REGISTER
R/W-0/0
R-0/0
SMP
CKE
D/A
PS
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
SMP:
SPI Data Input Sample bit
SPI Master mode:
1
= Input data sampled at end of data output time
0
= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2C Master or Slave mode:
1
= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0
= Slew rate control enabled for high speed mode (400 kHz)
bit 6
CKE:
SPI Clock Edge Select bit (SPI mode only)
In SPI Master or Slave mode:
1
= Transmit occurs on transition from active to Idle clock state
0
= Transmit occurs on transition from Idle to active clock state
In I2C mode only:
1
= Enable input logic so that thresholds are compliant with SM bus specification
0
= Disable SM bus specific inputs
bit 5
D/A:
Data/Address bit (I2C mode only)
1
= Indicates that the last byte received or transmitted was data
0
= Indicates that the last byte received or transmitted was address
bit 4
P:
Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1
= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0
= Stop bit was not detected last
bit 3
S:
Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1
= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0
= Start bit was not detected last
bit 2
R/W:
Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match
to the next Start bit, Stop bit, or not ACK bit.
In I2C Slave mode:
1
= Read
0
= Write
In I2C Master mode:
1
= Transmit is in progress
0
= Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.
bit 1
UA:
Update Address bit (10-bit I2C mode only)
1
= Indicates that the user needs to update the address in the SSPADD register
0
= Address does not need to be updated
bit 0
BF:
Buffer Full Status bit
Receive (SPI and I2C modes):
1
= Receive complete, SSPBUF is full
0
= Receive not complete, SSPBUF is empty
Transmit (I2C mode only):
1
= Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0
= Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
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