參數(shù)資料
型號(hào): PIC18LF258-I/SO
廠商: Microchip Technology
文件頁數(shù): 7/116頁
文件大?。?/td> 0K
描述: IC MCU CAN FLASH 16K LP 28-SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 27
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 1.5K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
PIC18FXX8
DS41159E-page 102
2006 Microchip Technology Inc.
9.4
PORTD, TRISD and LATD
Registers
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding Data Direction register for the port is TRISD.
Setting a TRISD bit (= 1) will make the corresponding
PORTD pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISD
bit (= 0) will make the corresponding PORTD pin an
output (i.e., put the contents of the output latch on the
selected pin).
Read-modify-write operations on the LATD register
read and write the latched output value for PORTD.
PORTD uses Schmitt Trigger input buffers. Each pin is
individually configurable as an input or output.
PORTD can be configured as an 8-bit wide, micro-
processor port (Parallel Slave Port or PSP) by setting
the control bit PSPMODE (TRISE<4>). In this mode,
the input buffers are TTL. See Section 10.0 “Parallel
Slave Port” for additional information.
PORTD is also multiplexed with the analog comparator
module and the ECCP module.
EXAMPLE 9-4:
INITIALIZING PORTD
FIGURE 9-9:
PORTD BLOCK DIAGRAM IN I/O PORT MODE
Note:
This
port
is
only
available
on
the
PIC18F448 and PIC18F458.
CLRF
PORTD
; Initialize PORTD by
; clearing output
; data latches
CLRF
LATD
; Alternate method
; to clear output
; data latches
MOVLW
07h
; comparator off
MOVWF
CMCON
MOVLW
0CFh
; Value used to
; initialize data
; direction
MOVWF
TRISD
; Set RD3:RD0 as inputs
; RD5:RD4 as outputs
; RD7:RD6 as inputs
PORT/PSP Select
Data Bus
WR LATD
WR TRISD
Data Latch
TRIS Latch
RD TRISD
Q
D
Q
CK
QD
EN
Q
D
Q
CK
P
N
VDD
Vss
RD PORTD
RD0/PSP0/
or
PORTD
RD LATD
Schmitt
Trigger
Note
1: I/O pins have diode protection to VDD and VSS.
PSP Data Out
PSP Write
PSP Read
C1IN+
C1IN+ pin(1)
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