![](http://datasheet.mmic.net.cn/Microchip-Technology/PIC18LF47J53T-I-ML_datasheet_99558/PIC18LF47J53T-I-ML_215.png)
2010 Microchip Technology Inc.
DS39774D-page 215
PIC18F85J11 FAMILY
FIGURE 17-24:
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESSING)
P
9
8
7
6
5
D0
D1
D2
D3
D4
D5
D6
D7
S
A7
A6
A5
A4
A3
A2
A1
SDA
SCL
1
2
34
5
6
78
9
1
23
4
5
6
7
8
9
12
3
4
B
u
sm
aster
ter
m
inate
s
tra
n
sfer
AC
K
Re
ce
ivin
g
Da
ta
fr
o
m
Sl
av
e
Re
ce
ivin
gDa
ta
fr
om
Sla
ve
D0
D1
D2
D3
D4
D5
D6
D7
ACK
R/W
=
1
T
ra
n
smi
tA
ddr
ess
to
S
lave
SSPI
F
BF
AC
K
is
not
sent
W
rit
e
to
SS
PCO
N
2
<
0
>
(
SEN
=
1
),
W
ri
te
to
S
P
B
U
F
occu
rs
her
e,
A
C
K
fr
o
m
Sl
a
ve
M
a
ster
confi
gured
as
a
r
e
cei
ver
by
pro
g
ram
m
ing
S
P
C
ON
2<
3>
(R
C
E
N
=
1
)
PE
N
b
it=
1
w
ri
tte
n
her
e
D
a
ta
sh
ifte
d
in
on
fal
ling
ed
ge
of
C
L
K
C
lear
ed
in
so
ftw
ar
e
st
ar
tX
M
IT
SEN
=
0
SSPO
V
SD
A
=
0
,S
C
L=
1
wh
ile
CPU
AC
K
Cle
a
re
d
in
so
ftwa
re
Cl
ea
re
din
so
ftwa
re
Se
tS
SPI
F
in
te
rr
up
t
at
end
of
re
cei
ve
Se
tP
b
it
(SSP
ST
A
T
<4
>)
an
d
S
P
IF
A
C
K
fro
m
Ma
ster
,
Se
tSS
PI
F
a
te
nd
S
e
tS
S
P
IF
inter
rup
t
at
end
o
fA
cknow
ledge
se
quence
S
et
S
P
IF
in
terr
upt
at
en
dof
A
cknow
le
dg
e
seque
nce
of
r
e
ceive
S
e
tA
C
K
E
N
,sta
rt
A
cknow
ledg
e
sequ
ence,
SDA
=
ACKDT
=
1
RCEN
cle
a
re
d
au
tom
a
tically
RCEN
=
1
,st
ar
t
ne
xt
r
e
ce
ive
W
rite
to
S
P
C
ON2<
4>
to
st
ar
tA
cknowledge
seque
n
ce,
SD
A
=
ACK
D
T
(
SSP
CO
N2
<5
>)
=
0
RCEN
cle
a
re
d
au
tom
a
tically
ACKEN
be
gi
n
S
tart
condi
tion
C
lear
ed
in
so
ftw
ar
e
SDA
=
A
C
KDT
=
0
La
st
bit
is
shif
ted
into
S
P
S
R
and
con
tent
sar
e
unl
o
aded
in
to
S
P
B
U
F
Cle
a
re
d
in
sof
twar
e
S
P
O
V
is
set
beca
use
S
SPB
UF
is
still
fu
ll
resp
onds
to
S
P
IF