![](http://datasheet.mmic.net.cn/Microchip-Technology/PIC18LF47J53T-I-ML_datasheet_99558/PIC18LF47J53T-I-ML_201.png)
2010 Microchip Technology Inc.
DS39774D-page 201
PIC18F85J11 FAMILY
FIGURE 17-13:
I2C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESSING)
SDA
SCL
SS
PI
F
(
P
IR
1
<
3
>
)
BF
(
S
SPS
TA
T
<
0
>
)
S
1
2
3
4
5
6
7
8
9
1
23
4
5
6
7
8
9
1
2
34
5
7
8
9
P
1
0
A
9A
8
A
7
A
6
A
5
A
4
A
3
A
2A
1A
0
11
1
0
A
8
R/W
=
1
ACK
AC
K
R/W
=
0
ACK
R
e
cei
ve
F
irst
B
yte
of
A
ddr
ess
Cle
ar
e
d
in
so
ftwa
re
B
u
sm
a
ster
ter
m
inat
es
tr
ansfer
A9
6
Re
ce
iv
e
Se
co
nd
By
te
o
fAd
dr
e
ss
C
le
a
red
by
har
d
w
a
re
w
hen
S
P
A
DD
is
u
p
da
te
d
with
lo
w
byte
of
addr
e
ss
UA
(
S
PST
A
T
<1
>)
Cl
ock
is
h
e
ld
lo
w
u
n
til
upda
te
of
S
P
A
D
has
ta
ken
pla
ce
UA
is
set
ind
icating
th
at
th
e
S
P
A
D
ne
eds
to
be
up
dated
UA
is
set
indica
ting
tha
t
S
P
A
D
ne
eds
to
be
upd
a
ted
C
leare
d
by
ha
rdw
a
re
w
h
en
S
P
A
DD
is
u
pd
a
te
dwi
th
h
ig
h
byte
o
fadd
ress.
S
SPB
UF
is
wr
itte
nwi
th
content
so
fS
S
P
S
R
Du
m
yr
e
a
d
o
fSS
PBUF
to
clear
B
F
flag
Rece
ive
F
irs
tB
yte
of
A
d
dr
ess
12
3
4
5
7
8
9
D7
D6
D5
D4
D3
D1
ACK
D2
6
T
ra
n
sm
itt
in
g
Da
ta
Byte
D0
Du
m
yr
e
a
d
o
fSS
PBUF
to
clear
B
F
flag
Sr
Cle
a
re
d
in
so
ftwa
re
Wr
ite
o
fS
SPB
UF
in
itia
te
str
a
n
sm
it
C
lear
ed
in
so
ftw
are
Co
m
p
le
tio
n
o
f
cl
ea
rs
B
F
flag
CKP
(
S
SPCO
N
1
<
4
>
)
CKP
is
se
tin
so
ftwa
re
CKP
is
a
u
to
m
a
tica
lly
cle
a
re
d
in
h
a
rd
wa
re
,h
o
ld
in
g
SCL
lo
w
Clo
ck
is
h
e
ld
lo
w
un
til
update
of
S
P
A
D
h
a
s
ta
ke
n
pl
ace
dat
a
tr
ansmi
ssi
on
Clo
ck
is
h
e
ld
lo
w
u
n
til
CK
P
is
set
to
‘1
’
thi
rd
addr
ess
sequ
ence
B
F
flag
is
cl
ea
r
at
the
end
of
the