參數(shù)資料
型號: PIC18LF4420-I/PT
廠商: Microchip Technology
文件頁數(shù): 20/151頁
文件大小: 0K
描述: IC MCU FLASH 8KX16 44TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 160
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 643 (CN2011-ZH PDF)
PIC16(L)F1782/3
DS41579C-page 288
Preliminary
2011-2012 Microchip Technology Inc.
26.5.3.3
7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPCON3 register
enables additional clock stretching and interrupt gen-
eration after the 8th falling edge of a received match-
ing address. Once a matching address has been
clocked in, CKP is cleared and the SSPIF interrupt is
set.
Figure 26-18 displays a standard waveform of a 7-bit
Address Slave Transmission with AHEN enabled.
1.
Bus starts Idle.
2.
Master sends Start condition; the S bit of SSP-
STAT is set; SSPIF is set if interrupt on Start
detect is enabled.
3.
Master sends matching address with R/W bit
set. After the 8th falling edge of the SCL line the
CKP bit is cleared and SSPIF interrupt is gener-
ated.
4.
Slave software clears SSPIF.
5.
Slave software reads ACKTIM bit of SSPCON3
register, and R/W and D/A of the SSPSTAT reg-
ister to determine the source of the interrupt.
6.
Slave reads the address value from the
SSPBUF register clearing the BF bit.
7.
Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSPCON2 register accordingly.
8.
Slave sets the CKP bit releasing SCL.
9.
Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPIF.
12. Slave loads value to transmit to the master into
SSPBUF setting the BF bit.
13. Slave sets the CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the 9th SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPCON2 register.
16. Steps 10-15 are repeated for each byte transmit-
ted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note:
SSPBUF cannot be loaded until after the
ACK.
Note:
Master must send a not ACK on the last
byte to ensure that the slave releases the
SCL line to receive a Stop.
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