參數(shù)資料
型號： PIC18LF4420-I/PT
廠商： Microchip Technology
文件頁數(shù)： 76/151頁
文件大小： 0K
描述： IC MCU FLASH 8KX16 44TQFP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝： 160
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，HLVD，POR，PWM，WDT
輸入/輸出數(shù)： 36
程序存儲器容量： 16KB（8K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 643 (CN2011-ZH PDF)
2011-2012 Microchip Technology Inc.
Preliminary
DS41579C-page 343
PIC16(L)F1782/3
27.5.2
SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for synchronous slave operation:
SYNC = 1
CSRC = 0
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART.
27.5.2.1
EUSART Synchronous Slave
Transmit
The operation of the Synchronous Master and Slave
modes
are
identical
(see
, except in the
case of the Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1.
The first character will immediately transfer to
the TSR register and transmit.
2.
The second word will remain in TXREG register.
3.
The TXIF bit will not be set.
4.
After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
5.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
27.5.2.2
Synchronous Slave Transmission
Set-up:
1.
Set the SYNC and SPEN bits and clear the
CSRC bit.
2.
Clear the ANSEL bit for the CK pin (if applicable).
3.
Clear the CREN and SREN bits.
4.
If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5.
If 9-bit transmission is desired, set the TX9 bit.
6.
Enable transmission by setting the TXEN bit.
7.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8.
Start transmission by writing the
Least
Significant 8 bits to the TXREG register.
TABLE 27-9:
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
APFCON
C2OUTSEL
CC1PSEL
SDOSEL
SCKSEL
SDISEL
TXSEL
RXSEL
CCP2SEL
BAUDCON
ABDOVF
RCIDL
—SCKP
BRG16
—
WUE
ABDEN
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
TXREG
EUSART Transmit Data Register
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
*
Page provides register information.
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