參數(shù)資料
型號: PIC18LF6620-I/PT
廠商: Microchip Technology
文件頁數(shù): 152/165頁
文件大小: 0K
描述: IC MCU FLSH 1MBIT W/AD LP 64TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 160
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 25MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 52
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 3.75K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
2004 Microchip Technology Inc.
DS39609B-page 85
PIC18F6520/8520/6620/8620/6720/8720
8.0
8 X 8 HARDWARE MULTIPLIER
8.1
Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18FXX20 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored in the 16-bit product register
pair (PRODH:PRODL). The multiplier does not affect
any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
Higher computational throughput
Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 8-1 shows a performance comparison between
enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
8.2
Operation
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 8-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 8-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
TABLE 8-1:
PERFORMANCE COMPARISON
MOVF
ARG1, W
;
MULWF
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF
ARG1, W
;
MULWF
ARG2
; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC
ARG2, SB
; Test Sign Bit
SUBWF
PRODH, F
; PRODH = PRODH
;
- ARG1
MOVF
ARG2, W
;
BTFSC
ARG1, SB
; Test Sign Bit
SUBWF
PRODH, F
; PRODH = PRODH
;
- ARG2
Routine
Multiply Method
Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz
@ 10 MHz
@ 4 MHz
8 x 8 unsigned
Without hardware multiply
13
69
6.9
s27.6 s69 s
Hardware multiply
1
100 ns
400 ns
1
s
8 x 8 signed
Without hardware multiply
33
91
9.1
s36.4 s91 s
Hardware multiply
6
600 ns
2.4
s6 s
16 x 16 unsigned
Without hardware multiply
21
242
24.2
s96.8 s242 s
Hardware multiply
28
2.8
s
11.2
s28 s
16 x 16 signed
Without hardware multiply
52
254
25.4
s
102.6
s254 s
Hardware multiply
35
40
4.0
s16.0 s40 s
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