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參數(shù)資料
| 型號： | PIC18LF6722-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 64KX16 64TQFP |
| 產(chǎn)品培訓模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標準包裝： | 160 |
| 系列： | PIC® 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復位，HLVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 54 |
| 程序存儲器容量： | 128KB（64K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 1K x 8 |
| RAM 容量： | 3.8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 12x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 644 (CN2011-ZH PDF) |
2006 Microchip Technology Inc.
DS80221C-page 9
PIC18F6627/6722/8627/8722
25. Module: EUSART
In rare situations, one or more extra zero bytes
have been observed in a packet transmitted by the
module operating in Asynchronous mode. The
actual data is not lost or corrupted; only unwanted
(extra) zero bytes are observed in the packet.
This situation has only been observed when the
contents of the transmit buffer, TXREGx, are trans-
ferred to the TSRx during the transmission of a
Stop bit. For this to occur, three things must
happen in the same instruction cycle:
TXREGx is written to;
the baud rate counter overflows (at the end of
the bit period); and
a Stop bit is being transmitted (shifted out of
TSRx).
Work around
If possible, do not use the module’s double buffer
capability. Instead, load the TXREGx register
when the TRMT bit (TXSTAx<1>) is set, indicating
the TSRx is empty.
If double-buffering is used and back-to-back
transmission is performed, then load TXREGx
immediately after TXxIF is set or wait 1-bit time after
TXxIF is set. Both solutions prevent writing TXREGx
while a Stop bit is transmitted. Note that TXxIF is set
at the beginning of the Stop bit transmission.
26. Module: EUSART
When performing back-to-back transmission in 9-bit
mode (TX9D bit in the TXSTAx register is set), the
second byte may be corrupted if it is written into
TXREGx immediately after the TMRT bit is set.
Work around
Execute a software delay, at least one-half the
transmission’s bit time, after TMRT is set and prior
to writing subsequent bytes into TXREGx.
Date Codes that pertain to this issue:
All engineering and production devices.
If transmission is intermittent, then do the following:
Wait for the TRMT bit to be set before
loading TXREGx
Alternatively, use a free timer resource to time
the baud period. Set up the timer to overflow
at the end of the Stop bit, then start the timer
when you load the TXREGx. Do not load the
TXREGx when timer is about to overflow.
Date Codes that pertain to this issue:
All engineering and production devices.
27. Module: EUSART
With the auto-wake-up option enabled by setting
the WUE (BAUDCONx<1>) bit, the RCxIF bit will
become set on a high-to-low transition on the RXx
pin. However, the WUE bit may not clear within
1TCY of a low-to-high transition on RXx. While the
WUE bit is set, reading the receive buffer,
RCREGx, will not clear the RCxIF interrupt flag.
Therefore, the first opportunity to automatically
clear RCxIF by reading RCREGx may take longer
than expected.
Work around
There are two work arounds available:
1. Clear the WUE bit in software, after the wake-
up event has occurred, prior to reading the
receive buffer, RCREGx.
2. Poll the WUE bit and read RCREGx after the
WUE bit is automatically cleared.
Date Codes that pertain to this issue:
All engineering and production devices.
28. Module: MSSP (SPI Mode)
In SPI mode, the SDOx output may change after
the inactive clock edge of the bit ‘0’ output. This
may affect some SPI components that read data
over 300 ns after the inactive edge of SCKx.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
Note:
RCxIF can only be cleared by reading
RCREGx.
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