參數(shù)資料
型號(hào): PIC18LF6722-I/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 4/16頁(yè)
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 64KX16 64TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 160
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 54
程序存儲(chǔ)器容量: 128KB(64K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 644 (CN2011-ZH PDF)
PIC18F6627/6722/8627/8722
DS80221C-page 12
2006 Microchip Technology Inc.
37. Module: Reset
This version of silicon does not support the func-
tionality described in Note 1 of parameter D002 in
Section 28.1 “DC Characteristics: Supply
Voltage” of the data sheet. The RAM content may
be altered during a Reset event if the following
conditions are met.
Device is accessing RAM.
Asynchronous Reset (i.e., WDT, BOR or MCLR
occurs when a write operation is being
executed (start of a Q4 cycle).
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
38. Module: External Memory Bus
The A<19:16> EMB address lines and Read/Write
control pins (OE, WRH and WRL) are released to
their respective inactive states at the same time,
violating
the
timing
condition
mentioned
in
Figure 28-8 and Figure 28-9 in the Device Data
Sheet. This may result in a peripheral device on
the bus detecting an address change when a write/
read is initiated. The bus capacitance and signal
delay on the address and control lines can affect
the probability of invalid detection.
Work around
Two work arounds are available:
1. Use a latch based on the falling edge of ALE to
hold the A<19:16> signals.
2. Add a delay circuit to extend the valid time for
A<19:16> signals to ensure the address is
valid until read/write signals go inactive.
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