參數(shù)資料
型號(hào): PIC24FJ64GA002-I/SP
廠商: Microchip Technology
文件頁(yè)數(shù): 4/52頁(yè)
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 64KB 28-DIP
產(chǎn)品培訓(xùn)模塊: Graphics LCD System and PIC24 Interface
Asynchronous Stimulus
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標(biāo)準(zhǔn)包裝: 15
系列: PIC® 24F
核心處理器: PIC
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,PMP,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲(chǔ)器容量: 64KB(22K x 24)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 647 (CN2011-ZH PDF)
配用: DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU
AC162088-ND - HEADER MPLAB ICD2 24FJ64GA004 28
AC164337-ND - MODULE SOCKET FOR PM3 40DIP
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
PIC24FJXXXGA0XX
DS39768D-page 12
2008 Microchip Technology Inc.
3.0
DEVICE PROGRAMMING – ICSP
ICSP mode is a special programming protocol that
allows you to read and write to PIC24FJXXXGA0XX
device family memory. The ICSP mode is the most
direct method used to program the device; note, how-
ever, that Enhanced ICSP is faster. ICSP mode also
has the ability to read the contents of executive
memory to determine if the programming executive is
present. This capability is accomplished by applying
control codes and instructions, serially to the device,
using pins, PGCx and PGDx.
In ICSP mode, the system clock is taken from the
PGCx pin, regardless of the device’s oscillator Config-
uration bits. All instructions are shifted serially into an
internal buffer, then loaded into the Instruction Register
(IR) and executed. No program fetching occurs from
internal memory. Instructions are fed in 24 bits at a
time. PGDx is used to shift data in and PGCx is used
as both the serial shift clock and the CPU execution
clock.
3.1
Overview of the Programming
Process
Figure 3-1 shows the high-level overview of the
programming process. After entering ICSP mode, the
first action is to Chip Erase the device. Next, the code
memory is programmed, followed by the device
Configuration registers. Code memory (including the
Configuration registers) is then verified to ensure that
programming was successful. Then, program the
code-protect Configuration bits, if required.
FIGURE 3-1:
HIGH-LEVEL ICSP
PROGRAMMING FLOW
3.2
ICSP Operation
Upon entry into ICSP mode, the CPU is Idle. Execution
of the CPU is governed by an internal state machine. A
4-bit control code is clocked in using PGCx and PGDx,
and this control code is used to command the CPU (see
The SIX control code is used to send instructions to the
CPU for execution, and the REGOUT control code is
used to read data out of the device via the VISI register.
TABLE 3-1:
CPU CONTROL CODES IN
ICSP MODE
Note:
During ICSP operation, the operating
frequency of PGCx must not exceed
10 MHz.
4-Bit
Control Code
Mnemonic
Description
0000b
SIX
Shift in 24-bit instruction
and execute.
0001b
REGOUT
Shift out the VISI (0784h)
register.
0010b-1111b
N/A
Reserved.
Start
Perform Chip
Erase
Program Memory
Verify Program
Done
Enter ICSP
Program Configuration Bits
Verify Configuration Bits
Exit ICSP
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