參數(shù)資料
型號： PIC24FJ64GA002-I/SP
廠商： Microchip Technology
文件頁數(shù)： 44/52頁
文件大小： 0K
描述： IC PIC MCU FLASH 64KB 28-DIP
產(chǎn)品培訓模塊： Graphics LCD System and PIC24 Interface
Asynchronous Stimulus
特色產(chǎn)品： PIC24FJ/33FJ MCUs & dsPIC? DSCs
標準包裝： 15
系列： PIC® 24F
核心處理器： PIC
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，PMP，SPI，UART/USART
外圍設備： 欠壓檢測/復位，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 21
程序存儲器容量： 64KB（22K x 24）
程序存儲器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-DIP（0.300"，7.62mm）
包裝： 管件
產(chǎn)品目錄頁面： 647 (CN2011-ZH PDF)
配用： DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU
AC162088-ND - HEADER MPLAB ICD2 24FJ64GA004 28
AC164337-ND - MODULE SOCKET FOR PM3 40DIP
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
2008 Microchip Technology Inc.
DS39768D-page 49
PIC24FJXXXGA0XX
7.0
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
Standard Operating Conditions
Operating Temperature: 0
°C to +70°C. Programming at +25°C is recommended.
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
D111
VDD
Supply Voltage During Programming
VDDCORE + 0.1
3.60
V
Normal programming(1,2)
D112
IPP
Programming Current on MCLR
—5
μA
D113
IDDP
Supply Current During Programming
—
2
mA
D031
VIL
Input Low Voltage
VSS
0.2 VDD
V
D041
VIH
Input High Voltage
0.8 VDD
VDD
V
D080
VOL
Output Low Voltage
—
0.4
V
IOL = 8.5 mA @ 3.6V
D090
VOH
Output High Voltage
3.0
—
V
IOH = -3.0 mA @ 3.6V
D012
CIO
Capacitive Loading on I/O pin (PGDx)
—
50
pF
To meet AC specifications
D013
CF
Filter Capacitor Value on VCAP
4.7
10
μF
Required for controller core
P1
TPGC
Serial Clock (PGCx) Period
100
—
ns
P1A
TPGCL
Serial Clock (PGCx) Low Time
40
—
ns
P1B
TPGCH
Serial Clock (PGCx) High Time
40
—
ns
P2
TSET1
Input Data Setup Time to Serial Clock
↑
15
—
ns
P3
THLD1
Input Data Hold Time from PGCx
↑
15
—
ns
P4
TDLY1
Delay Between 4-Bit Command and
Command Operand
40
—
ns
P4A
TDLY1A
Delay Between 4-Bit Command Operand
and Next 4-Bit Command
40
—
ns
P5
TDLY2
Delay Between Last PGCx
↓ of Command
Byte to First PGCx
↑ of Read of Data Word
20
—
ns
P6
TSET2VDD
↑ Setup Time to MCLR ↑
100
—
ns
P7
THLD2
Input Data Hold Time from MCLR
↑
25
—
ms
P8
TDLY3
Delay Between Last PGCx
↓ of Command
Byte to PGDx
↑ by Programming Executive
12
—
μs
P9
TDLY4
Programming Executive Command
Processing Time
40
—
μs
P10
TDLY6
PGCx Low Time After Programming
400
—
ns
P11
TDLY7
Chip Erase Time
400
—
ms
P12
TDLY8
Page Erase Time
40
—
ms
P13
TDLY9
Row Programming Time
2
—
ms
P14
TR
MCLR Rise Time to Enter ICSP mode
—
1.0
μs
P15
TVALID
Data Out Valid from PGCx
↑
10
—
ns
P16
TDLY10
Delay Between Last PGCx
↓ and MCLR ↓
0—
s
P17
THLD3MCLR
↓ to VDD ↓
100
—
ns
P18
TKEY1
Delay from First MCLR
↓ to First PGCx ↑
for Key Sequence on PGDx
40
—
ns
P19
TKEY2
Delay from Last PGCx
↓ for Key
Sequence on PGDx to Second MCLR
↑
1—
ms
P20
TDLY11
Delay Between PGDx
↓ by Programming
Executive to PGDx Driven by Host
23
—
s
P21
TDLY12
Delay Between Programming Executive
Command Response Words
8—
ns
Note 1:
VDDCORE must be supplied to the VDDCORE/VCAP pin if the on-chip voltage regulator is disabled. See Section 2.1
“Power Requirements” for more information. (Minimum VDDCORE allowing Flash programming is 2.25V.)
2:
VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within ±0.3V
of VDD and VSS, respectively.
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