參數(shù)資料
型號: PIC24HJ256GP610A-I/PT
廠商: Microchip Technology
文件頁數(shù): 16/84頁
文件大小: 0K
描述: IC MCU 16BIT 256KB FLASH 100TQFP
標準包裝: 119
系列: PIC® 24H
核心處理器: PIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: CAN,I²C,IrDA,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 85
程序存儲器容量: 256KB(85.5K x 24)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 32x10b/12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 托盤
2010 Microchip Technology Inc.
DS70152H-page 23
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
4.0
THE PROGRAMMING
EXECUTIVE
4.1
Programming Executive
Communication
The programmer and programming executive have a
master-slave relationship, where the programmer is
the master programming device and the programming
executive is the slave.
All communication is initiated by the programmer in the
form of a command. Only one command at a time can
be sent to the programming executive. In turn, the
programming executive only sends one response to
the programmer after receiving and processing a
command. The programming executive command set
Commands”. The response set is described in
4.1.1
COMMUNICATION INTERFACE
AND PROTOCOL
The ICSP/Enhanced ICSP interface is a 2-wire SPI
implemented using the PGCx and PGDx pins. The
PGCx pin is used as a clock input pin and the clock
source must be provided by the programmer. The PGDx
pin is used for sending command data to and receiving
response data from the programming executive.
FIGURE 4-1:
PROGRAMMING
EXECUTIVE SERIAL
TIMING
Since a 2-wire SPI is used, and data transmissions are
bidirectional, a simple protocol is used to control the
direction of PGDx. When the programmer completes a
command transmission, it releases the PGDx line and
allows the programming executive to drive this line
high. The programming executive keeps the PGDx line
high to indicate that it is processing the command.
After the programming executive has processed the
command, it brings PGDx low (P9b) to indicate to the
programmer that the response is available to be
clocked out. The programmer can begin to clock out
the response after maximum wait (P9b) and it must
provide the necessary amount of clock pulses to
receive the entire response from the programming
executive.
After the entire response is clocked out, the
programmer should terminate the clock on PGCx until
it is time to send another command to the programming
executive. This protocol is illustrated in Figure 4-2.
4.1.2
SPI RATE
In Enhanced ICSP mode, the dsPIC33F/PIC24H family
devices operate from the Fast Internal RC oscillator,
which has a nominal frequency of 7.3728 MHz. This
oscillator frequency yields an effective system clock
frequency of 1.8432 MHz. To ensure that the
programmer does not clock too fast, it is recommended
that a 1.85 MHz clock be provided by the programmer.
4.1.3
TIME OUTS
The programming executive uses no Watchdog or time
out for transmitting responses to the programmer. If the
programmer does not follow the flow control
mechanism using PGCx as described in Section 4.1.1
possible that the programming executive will behave
unexpectedly while trying to send a response to the
programmer. Since the programming executive has no
time out, it is imperative that the programmer correctly
follow the described communication protocol.
As a safety measure, the programmer should use the
command time outs identified in Table 4-1. If the
command time out expires, the programmer should
reset
the
programming
executive
and
start
programming the device again.
Note:
The Programming Executive (PE) can be
located within the following folder within
your installation of MPLAB IDE:
...\Microchip\MPLAB IDE\REAL ICE,
and then selecting the Hex PE file,
RIPE_01b_xxxxxx.hex.
Note:
For Enhanced ICSP, all serial data is
transmitted on the falling edge of PGCx
and latched on the rising edge of PGCx.
All data transmissions are sent to the Most
Significant bit first using 16-bit mode (see
PGCx
PGDx
12
3
11
13
15 16
14
12
LSb
14 13 12 11
45
6
MSb
1
2
3
...
4
5
P2
P3
P1
P1B
P1A
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