CHAPTER 7 16-BIT TIMER/EVENT COUNTER Q (TMQ)
User’s Manual U17716EJ2V0UD
240
Figure 7-1. TMQ0 Block Diagram
fXX
fXX/2
fXX/4
fXX/8
fXX/16
fXX/32
fXX/64
fXX/128
Internal bus
TQ0CNT
TQ0CCR0
CCR1
buffer
register
TQ0CCR1
TIQ00
EVTQ0
TIQ01
TIQ02
TIQ03
CCR0
buffer
register
TQ0CCR2
CCR3
buffer
register
TQ0CCR3
TOQH0OFF
CCR2
buffer
register
Clear
INTTQ0OV
TOQ00Note 1
TOQ01/TOQH01Note 2
TOQ02
TOQ03/TOQH02Note 2
TOQH03Note 2
INTTQ0CC0
INTTQ0CC1
INTTQ0CC2
INTTQ0CC3
16-bit counter
See Figure 7-2
TMQ0 Output Pin
Configuration
Selector
Edge
detector
Output
controller
Selector
Edge
detector
Edge
detector
Notes 1. If P16 is used as the TOQ00 output pin or an output port, when an error (oscillator stop) is detected
by the clock monitor, the CLMER signal (low level) is output from P16. Low-level output is released
by reset signal. For details, see Table 4-5 Alternate-Function Pins of Port 1.
2. When the TOQH01 to TOQH03 pins are selected, these pins can be set in the high-impedance state
by the TOQH0OFF pin input. For details, see 9.3 (6) High-impedance output control registers 00,
01, 10, 11 (HZAyCTLn).
Caution
The TOQH01 to TOQH03 pins are valid only in the PWM output mode.
Remark
fXX: Peripheral clock