2011
Micr
och
ip
T
e
chn
o
logy
Inc.
D
S
6
1143H-p
age
61
PIC32MX3XX/4XX
TABLE 4-12:
SPI1-2 REGISTERS MAP(1,2)
V
irtual
A
ddress
(BF80_#
)
Regis
ter
Na
m
e
Bit
Range
Bits
All
R
e
set
s
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
5800
SPI1CON
31:16
FRMEN
FRMSYNC FRMPOL
—
—SPIFE
—
0000
15:0
ON
—
SIDL
DISSDO
MODE32
MODE16
SMP
CKE
SSEN
CKP
MSTEN
—
0000
5810 SPI1STAT
31:16
—
0000
15:0
—
SPIBUSY
—
SPIROV
—
SPITBE
—
SPIRBF
0008
5820
SPI1BUF
31:16
DATA<31:0>
0000
15:0
0000
5830
SPI1BRG
31:16
—
0000
15:0
—
—BRG<8:0>
0000
5A00
SPI2CON
31:16
FRMEN
FRMSYNC FRMPOL
—
—SPIFE
—
0008
15:0
ON
—
SIDL
DISSDO
MODE32
MODE16
SMP
CKE
SSEN
CKP
MSTEN
—
0000
5A10 SPI2STAT
31:16
—
0000
15:0
—
SPIBUSY
—
SPIROV
—
SPITBE
—
SPIRBF
0008
5A20
SPI2BUF
31:16
DATA<31:0>
0000
15:0
0000
5A30
SPI2BRG
31:16
—
0000
15:0
—
—BRG<8:0>
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
1:
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV 2:
SPI2 Module is not present on PIC32MX420FXXXX/440FXXXX devices.