參數(shù)資料
型號(hào)： PIC32MX320F032HT-40V/MR
廠商： Microchip Technology
文件頁數(shù)： 34/214頁
文件大小： 0K
描述： IC MCU 32BIT 32KB FLASH 64QFN
標(biāo)準(zhǔn)包裝： 3,300
系列： PIC® 32MX
核心處理器： MIPS32? M4K?
芯體尺寸： 32-位
速度： 40MHz
連通性： I²C，IrDA，LIN，PMP，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 53
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 2.3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 64-VFQFN 裸露焊盤
包裝： 帶卷 (TR)
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2011 Microchip Technology Inc.
DS61143H-page 129
PIC32MX3XX/4XX
25.0
POWER-SAVING FEATURES
This
section
describes
power-saving
for
the
PIC32MX3XX/4XX. The PIC32MX devices offer a total
of nine methods and modes that are organized into two
categories that allow the user to balance power con-
sumption with device performance. In all of the meth-
ods and modes described in this section, power-saving
is controlled by software.
25.1
Power-Saving with CPU Running
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency, lower-
ing the PBCLK, and by individually disabling modules.
These methods are grouped into the following modes:
FRC Run mode: the CPU is clocked from the FRC
clock source with or without postscalers.
LPRC Run mode: the CPU is clocked from the
LPRC clock source.
SOSC Run mode: the CPU is clocked from the
SOSC clock source.
Peripheral Bus Scaling mode: peripherals are
clocked at programmable fraction of the CPU
clock (SYSCLK).
25.2
CPU Halted Methods
The device supports two power-saving modes, Sleep
and Idle, both of which halt the clock to the CPU. These
modes operate with all clock sources, as listed below:
POSC Idle Mode: the system clock is derived from
the POSC. The system clock source continues to
operate.
Peripherals continue to operate, but can
optionally be individually disabled.
FRC Idle Mode: the system clock is derived from
the FRC with or without postscalers. Peripherals
continue to operate, but can optionally be
individually disabled.
SOSC Idle Mode: the system clock is derived from
the SOSC. Peripherals continue to operate, but
can optionally be individually disabled.
LPRC Idle Mode: the system clock is derived from
the LPRC.
Peripherals continue to operate, but can option-
ally be individually disabled. This is the lowest
power mode for the device with a clock running.
Sleep Mode: the CPU, the system clock source,
and any peripherals that operate from the system
clock source, are halted.
Some peripherals can operate in Sleep using spe-
cific clock sources. This is the lowest power mode
for the device.
25.3
Power-Saving Operation
The purpose of all power-saving is to reduce power
consumption by reducing the device clock frequency.
To achieve this, low-frequency clock sources can be
selected. In addition, the peripherals and CPU can be
halted
or
disabled
to
further
reduce
power
consumption.
25.3.1
SLEEP MODE
Sleep mode has the lowest power consumption of the
device Power-Saving operating modes. The CPU and
most peripherals are halted. Select peripherals can
continue to operate in Sleep mode and can be used to
wake the device from Sleep. See the individual periph-
eral module sections for descriptions of behavior in
Sleep mode.
Sleep mode includes the following characteristics:
The CPU is halted.
The system clock source is typically shut down.
information.
There can be a wake-up delay based on the
oscillator selection.
The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode.
The BOR circuit, if enabled, remains operative
during Sleep mode.
The WDT, if enabled, is not automatically cleared
prior to entering Sleep mode.
Some peripherals can continue to operate in
Sleep mode. These peripherals include I/O pins
that detect a change in the input signal, WDT,
ADC, UART and peripherals that use an external
clock input or the internal LPRC oscillator, e.g.,
RTCC and Timer 1.
I/O pins continue to sink or source current in the
same manner as they do when the device is not in
Sleep.
The USB module can override the disabling of the
POSC or FRC. Refer to Section 11.0 “USB On-
The-Go (OTG)” for specific details.
Some modules can be individually disabled by
software prior to entering Sleep in order to further
reduce consumption.
Note 1: This data sheet summarizes the features
of
the
PIC32MX3XX/4XX
family
of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 10. “Power-Saving
Features” (DS61130) of the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available
on
all
devices.
Refer
to
this data sheet for device-specific register
and bit information.
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