參數(shù)資料
型號: PIC32MX664F064L-I/BG
廠商: Microchip Technology
文件頁數(shù): 5/12頁
文件大小: 0K
描述: MCU PIC 64KB FLASH 121XBGA
特色產(chǎn)品: PIC32 32-Bit MCU Families
標準包裝: 184
系列: PIC® 32MX
核心處理器: MIPS32? M4K?
芯體尺寸: 32-位
速度: 80MHz
連通性: 以太網(wǎng),I²C,SPI,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 121-TFBGA
包裝: 托盤
PIC32MX534/564/664/764
DS80511G-page 2
2010-2012 Microchip Technology Inc.
TABLE 2:
SILICON ISSUE SUMMARY
Module
Feature
Item
#
Issue Summary
Affected
Revisions(1)
A0
A1
A2
On 64-pin devices the TMS pin requires an external pull-
up.
XXX
The TXBAT bit status may be incorrect after an abort.
X
Slave Mode
The SPIBUSY status is incorrect after an aborted
transfer.
XXX
Slave Mode
A wake-up interrupt may not be clearable.
X
Frame Mode
Recovery from an underrun requires multiple SPI clock
periods.
XXX
Byte writes to the SPISTAT register are not decoded
correctly.
XXX
The TRMT bit is asserted before the transmission is
complete.
XXX
IrDA with BCLK
TX data is corrupted when BRG values greater than
0x200 are used.
XXX
IrDA
The IrDA minimum bit time is not detected at all baud
rates.
XXX
UART Receive Buffer
Overrun Error Status
OERR bit does not get cleared on a module Reset.
X
Conversion Trigger
from INT0 Interrupt
The ADC module conversion triggers occur on the rising
edge of the INT0 signal even when INT0 is configured to
generate an interrupt on the falling edge.
XXX
Boundary Scan
Pin 100 on 100-pin packages and pin A1 on 121-pin
packages do not respond to boundary scan commands.
XXX
Clock Switch
Clock switch may not work if Cache is disabled and
Prefetch is enabled.
XXX
Suspend Status
The DMABUSY status bit may not reflect the correct
status if the DMA module is suspended.
XXX
BOR
Device may not exit BOR state if BOR event occurs.
X
OTG Mode
When the USB model is configured for OTG operation, it
may not properly recognize all required OTG voltage
levels on VBUS pin.
XXX
Clock Switch
If a Fail-Safe Clock Monitor (FSCM) event occurs when
Primary Oscillator (POSC) mode is used, firmware clock
switch requests to switch from FRC mode will fail.
XXX
Slave Mode
The I2C module does not respond to address 0x78 when
the STRICT and A10M bits are cleared in the I2CxCON
register.
XXX
UIDLE Interrupt
UIDLE interrupts cease if the UIDLE interrupt flag is
cleared.
XXX
Constant Data
Access from Flash
A Data Bus Exception (DBE) may occur if an interrupt is
encountered by the CPU while it is accessing constant
data from Flash memory.
XXX
Data Write to a
Peripheral
A data write operation by the CPU to a peripheral may
be repeated if an interrupt occurs during initial write
operation.
XXX
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.
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