參數(shù)資料
型號(hào): PIC32MX695F512H-80I/MR
廠商: Microchip Technology
文件頁(yè)數(shù): 53/64頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT 512KB FLASH 64QFN
特色產(chǎn)品: 32-Bit PIC? Microcontroller
PIC32 32-Bit MCU Families
標(biāo)準(zhǔn)包裝: 40
系列: PIC® 32MX
核心處理器: MIPS32? M4K?
芯體尺寸: 32-位
速度: 80MHz
連通性: 以太網(wǎng),I²C,SPI,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 650 (CN2011-ZH PDF)
2007-2012 Microchip Technology Inc.
DS61145K-page 57
PIC32MX
20.0
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
TABLE 20-1:
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
Standard Operating Conditions
Operating Temperature: 0C to +70C. Programming at +25C is recommended.
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
D111
VDD
Supply Voltage During Programming
V
See Note 1
D113
IDDP
Supply Current During Programming
mA
See Note 1
D114
IPEAK
Instantaneous Peak Current During Start-up
mA
See Note 1
D031
VIL
Input Low Voltage
V
See Note 1
D041
VIH
Input High Voltage
V
See Note 1
D080
VOL
Output Low Voltage
V
See Note 1
D090
VOH
Output High Voltage
V
See Note 1
D012
CIO
Capacitive Loading on I/O pin (PGEDx)
pF
See Note 1
D013
CF
Filter Capacitor Value on VCAP
——
μF
See Note 1
P1
TPGC
Serial Clock (PGECx) Period
100
ns
P1A
TPGCL
Serial Clock (PGECx) Low Time
40
ns
P1B
TPGCH
Serial Clock (PGECx) High Time
40
ns
P6
TSET2VDD
↑ Setup Time to MCLR ↑
100
ns
P7
THLD2
Input Data Hold Time from MCLR
500
ns
P9A
TDLY4
PE Command Processing Time
40
μs—
P9B
TDLY5
Delay between PGEDx
↓ by the PE to PGEDx
Released by the PE
15
μs—
P11
TDLY7
Chip Erase Time
ms
See Note 1
P12
TDLY8
Page Erase Time
ms
See Note 1
P13
TDLY9
Row Programming Time
ms
See Note 1
P14
TR
MCLR Rise Time to Enter ICSP mode
1.0
μs—
P15
TVALID
Data Out Valid from PGECx
10
ns
P16
TDLY8
Delay between Last PGECx
↓ and MCLR ↓
0—
s
P17
THLD3MCLR
↓ to VDD
100
ns
P18
TKEY1
Delay from First MCLR
↓ to First PGECx ↑ for Key
Sequence on PGEDx
40
ns
P19
TKEY2
Delay from Last PGECx
↓ for Key Sequence on
PGEDx to Second MCLR
40
ns
P20
TMCLRH MCLR High Time
500
s
Note 1:
Refer to the “Electrical Characteristics” chapter in the specific device data sheet for the Minimum and
Maximum values for this parameter.
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