參數(shù)資料
型號: PIC32MX695F512H-80I/MR
廠商: Microchip Technology
文件頁數(shù): 8/64頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 512KB FLASH 64QFN
特色產(chǎn)品: 32-Bit PIC? Microcontroller
PIC32 32-Bit MCU Families
標準包裝: 40
系列: PIC® 32MX
核心處理器: MIPS32? M4K?
芯體尺寸: 32-位
速度: 80MHz
連通性: 以太網(wǎng),I²C,SPI,UART/USART,USB OTG
外圍設備: 欠壓檢測/復位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 托盤
產(chǎn)品目錄頁面: 650 (CN2011-ZH PDF)
PIC32MX
DS61145K-page 16
2007-2012 Microchip Technology Inc.
6.3
XferData
Pseudo Operation
Format:
oData = XferData (iData)
Purpose:
To clock data to and from the register selected by the
command.
Description (in sequence):
1.
The TMS Header is clocked into the device to
select the Shift DR state.
2.
The data is clocked in/out of the device on
TDI/TDO while holding signal TMS low.
3.
The last MSb of the data is clocked in/out
while setting TMS high.
4.
The TMS Footer is clocked in on TMS to return
the TAP controller to the Run/Test Idle state.
Restrictions:
None.
Example:
oData = XferData (32’h0x12)
FIGURE 6-5:
XferData 4-WIRE
FIGURE 6-6:
XferData 2-WIRE (4-PHASE)
TMS
TDI
TDO
iMSb
‘1’
TCK
‘1’
‘0’
iLSb
TMS Header = 100
Data (32’h0x12) Data (MSb) + TMS =1
TMS Footer = 10
oMSb
oLSb
TDI = 0
TMS = 0
TDO = oLSb
TDI = 0
TDO = X
TMS = 0
TDI = 0
TDO = X
TMS = 1
PGEC
PGED
TMS Header = 100
TDI = 0
TMS = 0
TDO = X
TDI = 0
TDO = X
TMS = 1
TDO = X
TMS = 0
TDI = iLSb
TDO = oLSb+1
TDI = iMSb
Data (31’h0x12) + TMS = 0
Data (MSb) + TMS Footer = 1
TMS Footer = 10
...
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