參數(shù)資料
型號: PIC32MX695F512H-80I/PT
廠商: Microchip Technology
文件頁數(shù): 20/64頁
文件大小: 0K
描述: IC MCU 32BIT 512KB FLASH 64TQFP
特色產(chǎn)品: 32-Bit PIC? Microcontroller
PIC32 32-Bit MCU Families
標準包裝: 160
系列: PIC® 32MX
核心處理器: MIPS32? M4K?
芯體尺寸: 32-位
速度: 80MHz
連通性: 以太網(wǎng),I²C,SPI,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測/復位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 650 (CN2011-ZH PDF)
配用: 876-1000-ND - PIC32 BREAKOUT BOARD
2007-2012 Microchip Technology Inc.
DS61145K-page 27
PIC32MX
13.0
INITIATING A FLASH ROW
WRITE
Once a row of data has been downloaded into the
device’s SRAM, the programming sequence must be
initiated to write the block of data to Flash memory.
13.1
With the PE
When using the PE, the data is immediately written to
the Flash memory from the SRAM. No further action is
required.
13.2
Without the PE
Flash memory write operations are controlled by the
NVMCON register. Programming is performed by set-
ting NVMCON to select the type of write operation and
initiating the programming sequence by setting the WR
control bit (NVMCON<15>).
FIGURE 13-1:
INITIATING FLASH WRITE
WITHOUT THE PE
The following steps are required to initiate a Flash
write:
1.
XferInstruction
(op code).
2.
Repeat Step 1 until the last instruction is
transferred to the CPU.
Start Operation
Unlock Flash Controller
Load Addresses in NVM Registers
Select Write Operation
Unprotect Control Registers
Done
TABLE 13-1:
INITIATE FLASH ROW WRITE
OP CODES
Op code
Instruction
Step 1: Initialize some constants.
3c04bf80
3484f400
34054003
34068000
34074000
3c11aa99
36316655
3c125566
365299aa
3c13ff20
3c100000
lui a0,0xbf80
ori a0,a0,0xf400
ori a1,$0,0x4003
ori a2,$0,0x8000
ori a3,$0,0x4000
lui s1,0xaa99
ori s1,s1,0x6655
lui s2,0x5566
ori s2,s2,0x99aa
lui s3,0xff20
lui s0,0x0000
Step 2: Set NVMADDR with the address of the
Flash row to be programmed.
3c08<ADDR>
3508<ADDR>
ac880020
lui t0,<FLASH_ROW_ADDR(31:16)>
ori t0,t0,<FLASH_ROW_ADDR(15:0)>
sw
t0,32(a0)
Step 3: Set NVMSRCADDR with the physical
source SRAM address.
3610<ADDR>
ac900040
ori s0,s0,<RAM_ADDR(15:0)>
sw
s0,64(a0)
Step 4: Set up NVMCON for write operation and poll
LVDSTAT.
ac850000
8C880000
31080800
1500fffd
00000000
sw
a1,0(a0)
delay (6 s)
here1:
lw
t0,0(a0)
andit0,t0,0x0800
bne t0,$0,<here1>
nop
Step 5: Unlock NVMCON and start write operation.
ac910010
ac920010
ac860008
sw
s1,16(a0)
sw
s2,16(a0)
sw
a2,8(a0)
Step 6: Repeatedly read the NVMCON register and
poll for WR bit to get cleared.
8c880000
01064024
1500fffd
00000000
here2:
lw
t0,0(a0)
and t0,t0,a2
bne t0,$0,<here2>
nop
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