參數(shù)資料
型號(hào): PIC32MX695F512H-80I/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 45/64頁(yè)
文件大小: 0K
描述: IC MCU 32BIT 512KB FLASH 64TQFP
特色產(chǎn)品: 32-Bit PIC? Microcontroller
PIC32 32-Bit MCU Families
標(biāo)準(zhǔn)包裝: 160
系列: PIC® 32MX
核心處理器: MIPS32? M4K?
芯體尺寸: 32-位
速度: 80MHz
連通性: 以太網(wǎng),I²C,SPI,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 650 (CN2011-ZH PDF)
配用: 876-1000-ND - PIC32 BREAKOUT BOARD
2007-2012 Microchip Technology Inc.
DS61145K-page 5
PIC32MX
4.0
CONNECTING TO THE DEVICE
The PIC32MX family provides two possible physical
interfaces for connecting to and programming the
memory contents (Figure 4-1). For all programming
interfaces, the target device must be properly powered
and all required signals must be connected. In addition,
the interface must be enabled, either through its Con-
figuration bit, as in the case of the JTAG 4-wire inter-
face, or though a special initialization sequence, as is
the case for the 2-wire ICSP interface.
The JTAG interface is enabled by default in blank
devices shipped from the factory.
Enabling ICSP is described in Section 7.0 “Entering
FIGURE 4-1:
PROGRAMMING
INTERFACES
4.1
4-wire Interface
One possible interface is the 4-wire JTAG (IEEE
1149.1) port. Table 4-1 lists the required pin connec-
tions. This interface uses the following four communi-
cation lines to transfer data to and from the PIC32MX
device being programmed:
TCK – Test Clock Input
TMS – Test Mode Select Input
TDI – Test Data Input
TDO – Test Data Output
These signals are described in the following four sec-
tions. Refer to the specific device data sheet for the
connection of the signals to the chip pins.
4.1.1
TEST CLOCK INPUT (TCK)
TCK is the clock that controls the updating of the TAP
controller and the shifting of data through the Instruc-
tion or selected Data register(s). TCK is independent of
the processor clock with respect to both frequency and
phase.
4.1.2
TEST MODE SELECT INPUT (TMS)
TMS is the control signal for the TAP controller. This
signal is sampled on the rising edge of TCK.
4.1.3
TEST DATA INPUT (TDI)
TDI is the test data input to the Instruction or selected
Data register(s). This signal is sampled on the rising
edge of TCK for some TAP controller states.
4.1.4
TEST DATA OUTPUT (TDO)
TDO is the test data output from the Instruction or Data
register(s). This signal changes on the falling edge of
TCK. TDO is only driven when data is shifted out,
otherwise the TDO is tri-stated.
TABLE 4-1:
4-WIRE INTERFACE PINS
Programmer
2-wire
ICSP
OR
4-wire
JTAG
+ MCLR, VDD, VSS
PIC32
Device Pin Name
Pin Type
Pin Description
MCLR
I
Programming Enable
ENVREG(2)
I
Enable for On-Chip Voltage Regulator
VDD and AVDD(1)
P
Power Supply
VSS and AVSS(1)
P
Ground
VCAP
P
CPU logic filter capacitor connection
TDI
I
Test Data In
TDO
O
Test Data Out
TCK
I
Test Clock
TMS
I
Test Mode State
Legend: I = Input
O = Output
P = Power
Note 1:
All power supply and ground pins must be connected, including analog supplies (AVDD) and ground
(AVSS).
2:
The ENVREG pin is not available on all devices. Please refer to the “Pin Diagrams” section in the
specific device data sheet to determine availability.
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