參數(shù)資料
型號: PK10N512VLK100
廠商: Freescale Semiconductor
文件頁數(shù): 15/71頁
文件大?。?/td> 0K
描述: IC ARM CORTEX MCU 512K 80-LQFP
產品培訓模塊: Kinetis® Cortex-M4 Microcontroller Family
標準包裝: 1
系列: Kinetis
核心處理器: ARM? Cortex?-M4
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,I²C,IrDA,SDHC,SPI,UART/USART
外圍設備: DMA,I²S,LVD,POR,PWM,WDT
輸入/輸出數(shù): 56
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 27x16b,D/A 1x12b
振蕩器型: 內部
工作溫度: -40°C ~ 105°C
封裝/外殼: 80-LQFP
包裝: 托盤
2.
Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3.
Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Low pulse width
2
ns
Twh
High pulse width
2
ns
Tr
Clock and data rise time
3
ns
Tf
Clock and data fall time
3
ns
Ts
Data setup
3
ns
Th
Data hold
2
ns
Figure 3. TRACE_CLKOUT specifications
Th
Ts
Th
TRACE_CLKOUT
TRACE_D[3:0]
Figure 4. Trace data specifications
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
22
Freescale Semiconductor, Inc.
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