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| 型號(hào)： | PK10N512VLK100 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 43/71頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM CORTEX MCU 512K 80-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Kinetis® Cortex-M4 Microcontroller Family |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Kinetis |
| 核心處理器： | ARM? Cortex?-M4 |
| 芯體尺寸： | 32-位 |
| 速度： | 100MHz |
| 連通性： | CAN，EBI/EMI，I²C，IrDA，SDHC，SPI，UART/USART |
| 外圍設(shè)備： | DMA，I²S，LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 56 |
| 程序存儲(chǔ)器容量： | 512KB（512K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 128K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.71 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 27x16b，D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 托盤 |
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6.6.3.2 12-bit DAC operating behaviors
Table 33. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL
P
Supply current — low-power mode
—
150
μA
IDDA_DACH
P
Supply current — high-speed mode
—
700
μA
tDACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
—
100
200
μs
tDACHP
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
—
15
30
μs
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08)
— low-power mode and high-speed mode
—
0.7
1
μs
Vdacoutl DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
—
100
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
100
—
VDACR
mV
INL
Integral non-linearity error — high speed
mode
—
±8
LSB
DNL
Differential non-linearity error — VDACR > 2
V
—
±1
LSB
DNL
Differential non-linearity error — VDACR =
VREF_OUT
—
±1
LSB
VOFFSET Offset error
—
±0.4
±0.8
%FSR
EG
Gain error
—
±0.1
±0.6
%FSR
PSRR
Power supply rejection ratio, VDDA ≥ 2.4 V
60
—
90
dB
TCO
Temperature coefficient offset voltage
—
3.7
—
μV/C
TGE
Temperature coefficient gain error
—
0.000421
—
%FSR/C
Rop
Output resistance load = 3 kΩ
—
250
Ω
SR
Slew rate -80h→ F7Fh→ 80h
High power (SPHP)
Low power (SPLP)
1.2
0.05
1.7
0.12
—
V/μs
CT
Channel to channel cross talk
—
-80
dB
BW
3dB bandwidth
High power (SPHP)
Low power (SPLP)
550
40
—
kHz
1. Settling within ±1 LSB
2. The INL is measured for 0 + 100 mV to VDACR 100 mV
3. The DNL is measured for 0 + 100 mV to VDACR 100 mV
4. The DNL is measured for 0 + 100 mV to VDACR 100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to
0x800, temperature range is across the full range of the device
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
48
Freescale Semiconductor, Inc.
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| PK10N512VLK100R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:K10 Sub-Family Data Sheet |
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| PK10N512VLK150R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:K10 Sub-Family Data Sheet |
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