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參數(shù)資料
型號: PK10N512VLL100
廠商: Freescale Semiconductor
文件頁數(shù): 27/71頁
文件大?。?/td> 0K
描述: IC ARM CORTEX MCU 512K 100-LQFP
產(chǎn)品培訓模塊: Kinetis® Cortex-M4 Microcontroller Family
標準包裝: 1
系列: Kinetis
核心處理器: ARM? Cortex?-M4
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,I²C,IrDA,SDHC,SPI,UART/USART
外圍設備: DMA,I²S,LVD,POR,PWM,WDT
輸入/輸出數(shù): 70
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 29x16b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 100-LQFP
包裝: 托盤
Table 23. NVM reliability specifications (continued)
Symbol
Description
Min.
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
5
50
years
tnvmretp1k Data retention after up to 1 K cycles
20
100
years
nnvmcycp Cycling endurance
10 K
50 K
cycles
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
6.4.2 EzPort Switching Specifications
Table 24. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
EP1
EZP_CK frequency of operation (all commands except
READ)
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
ns
EP5
EZP_D input valid to EZP_CK high (setup)
2
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
ns
EP7
EZP_CK low to EZP_Q output valid
16
ns
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
ns
EP9
EZP_CS negation to EZP_Q tri-state
12
ns
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
33
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