參數(shù)資料
型號: PK30N512VLQ100
廠商: Freescale Semiconductor
文件頁數(shù): 52/74頁
文件大?。?/td> 0K
描述: IC ARM CORTEX MCU 512K 144-LQFP
產(chǎn)品培訓(xùn)模塊: Kinetis® Cortex-M4 Microcontroller Family
標(biāo)準(zhǔn)包裝: 1
系列: Kinetis
核心處理器: ARM? Cortex?-M4
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,I²C,IrDA,SDHC,SPI,UART/USART
外圍設(shè)備: DMA,I²S,LCD,LVD,POR,PWM,WDT
輸入/輸出數(shù): 102
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 128K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 37x16b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 144-LQFP
包裝: 托盤
First data
Last data
First data
Data
Last data
Data
DS15
DS10
DS9
DS16
DS11
DS12
DS14
DS13
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Figure 22. DSPI classic SPI timing — slave mode
6.8.4 Inter-Integrated Circuit Interface (I2C) timing
Table 42. I 2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Unit
Minimum
Maximum
Minimum
Maximum
SCL Clock Frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
0.6
s
LOW period of the SCL clock
tLOW
4.7
1.3
s
HIGH period of the SCL clock
tHIGH
4
0.6
s
Set-up time for a repeated START
condition
tSU; STA
4.7
0.6
s
Data hold time for I2C bus devices
tHD; DAT
01
03
0.91
s
Data set-up time
tSU; DAT
1002, 5
ns
Rise time of SDA and SCL signals
tr
1000
20 +0.1Cb6
300
ns
Fall time of SDA and SCL signals
tf
300
20 +0.1Cb5
300
ns
Set-up time for STOP condition
tSU; STO
4
0.6
s
Bus free time between STOP and
START condition
tBUF
4.7
1.3
s
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
0
50
ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10ns and Output Load = 50pf
4. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
Peripheral operating requirements and behaviors
K30 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
56
Freescale Semiconductor, Inc.
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