參數(shù)資料
型號: PK60X256VLL100
廠商: Freescale Semiconductor
文件頁數(shù): 32/76頁
文件大小: 0K
描述: IC ARM CORTEX MCU 256K 100-LQFP
產(chǎn)品培訓(xùn)模塊: Kinetis® Cortex-M4 Microcontroller Family
標(biāo)準(zhǔn)包裝: 1
系列: Kinetis
核心處理器: ARM? Cortex?-M4
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,IrDA,SDHC,SPI,UART/USART,USB,USB OTG
外圍設(shè)備: DMA,I²S,LVD,POR,PWM,WDT
輸入/輸出數(shù): 66
程序存儲器容量: 256KB(256K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 25x16b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 100-LQFP
包裝: 托盤
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Figure 10. EzPort Timing Diagram
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 25. Flexbus limited voltage range switching specifications
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
2.7
3.6
V
Frequency of operation
FB_CLK
MHz
FB1
Clock period
20
ns
FB2
Address, data, and control output valid
11.5
ns
FB3
Address, data, and control output hold
0.5
ns
FB4
Data and FB_TA input setup
8.5
ns
FB5
Data and FB_TA input hold
0.5
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
Peripheral operating requirements and behaviors
K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
38
Freescale Semiconductor, Inc.
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