參數(shù)資料
型號(hào): PLC18V8Z35DH
廠商: NXP SEMICONDUCTORS
元件分類: PLD
英文描述: Zero standby power CMOS versatile PAL devices
中文描述: OT PLD, 35 ns, PDSO20
封裝: 4.40 MM, PLASTIC, MO-153AC, SOT-360-1, TSSOP-20
文件頁數(shù): 16/23頁
文件大?。?/td> 225K
代理商: PLC18V8Z35DH
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VNAME
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CUSTOMER NAME
PURCHASE ORDER #
PHILIPS DEVICE #
CF(XXXX)
CUSTOMER SYMBOLIZED PART #
TOTAL NUMBER OF PARTS
PROGRAM TABLE #
REV.
DATE
NOTES:
In the unprogrammed or virgin state:
All AND gate locations are pulled to a logic “0” (Low).
Output polarity is inverting.
Pins 1 and 11 are configured as inputs 0 and 9, respectively, via
the configuration cell. The clock and OE functions are disabled.
All output macro cells (OMC) are configured as combinatorial I/O,
with the outputs disabled via the direction control term.
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