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參數(shù)資料
| 型號： | PLL103-02 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS |
| 中文描述： | DDR SDRAM的緩沖器，用于4 DDR內(nèi)存臺式機 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 208K |
| 代理商： | PLL103-02 |
PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 11/07/00 Page 1
FEATURES
Generates 24 output buffer from one input.
Supports up to four DDR DIMMS or 2 SDRAM
DIMMS.
Supports 266MHz DDR SDRAM.
One additional output for feedback.
Less than 5ns delay.
Skew between any outputs is less than 100 ps.
2.5V or 3.3V Supply range.
Enhanced DDR and SDRAM Output Drive
selected by I2C.
Available in 48 pin SSOP.
BLOCK DIAGRAM
PIN CONFIGURATION
Note:
#: Active Low
DESCRIPTIONS
The PLL103-02 is designed as a 3.3V/2.5V buffer to
distribute high-speed clocks in PC applications. The
device has 24 outputs. These outputs can be
configured to support four unbuffered DDR DIMMS
or to support 2 unbuffered standard SDRAM DIMMS
and 2 DDR DIMMS. The PLL103-02 can be used in
conjunction with the PLL202-04 or similar clock
synthesizer for the VIA Pro 266 chipset.
The PLL103-02 also has an I2C interface, which can
enable or disable each output clock. When power up,
all output clocks are enabled (has internal pull up).
P
DDR5C
DDR4C_SDRAM7
DDR4T_SDRAM6
GND
VDD3.3_2.5
DDR3C_SDRAM5
DDR3T_SDRAM4
GND
VDD3.3_2.5
BUF_IN
DDR2C_SDRAM3
GND
VDD3.3_2.5
DDR1C_SDRAM1
DDR0C
DDR0T
GND
VDD3.3_2.5
FBOUT
SDATA
VDD3.3_2.5
DDR5T
DDR2T_SDRAM2
DDR10C
VDD2.5
GND
DDR9T
DDR9C
VDD2.5
PD#
GND
DDR8T
DDR8C
VDD2.5
GND
DDR7T
DDR7C
SEL_DDR
VDD2.5
GND
DDR11T
DDR11C
DDR10T
DDR6T
DDR6C
GND
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
41
42
44
43
45
46
47
48
DDR1T_SDRAM0
BUF_IN
SDATA
SCLK
I2C
Control
PD#
DDR0T
DDR0C
DDR1T_SDRAM0
DDR1C_SDRAM1
DDR2T_SDRAM2
DDR2C_SDRAM3
DDR3T_SDRAM4
DDR3C_SDRAM5
DDR4T_SDRAM6
DDR4C_SDRAM7
DDR5T
DDR5C
DDR6T
DDR6C
DDR7T
DDR7C
DDR8T
DDR8C
DDR9T
DDR9C
DDR10T
DDR10C
DDR11T
DDR11C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PLL103-02XC | DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS |
| PLL103-02XI | DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS |
| PLL103-02XM | DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS |
| PLL1100A | PHASE LOCKED LOOP |
| PLL1456A | PHASE LOCKED LOOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLL103-02D | 制造商:PLL 制造商全稱:PLL 功能描述:DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS |
| PLL103-02XC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS |
| PLL103-02XC-R | 制造商:PLL 制造商全稱:PLL 功能描述:DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS |
| PLL103-02XI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS |
| PLL103-02XM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS |
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