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參數(shù)資料
| 型號： | PLL103-02XC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS |
| 中文描述： | DDR SDRAM的緩沖器，用于4 DDR內(nèi)存臺式機 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大小： | 208K |
| 代理商： | PLL103-02XC |
PLL103-02
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 11/07/00 Page 3
Address Assignment
A6 A5 A4 A3 A2 A1 A0 R/W
1 0 1 0 0 1 _
Receiver/Transmitter
Data Transfer Rate
Provides both slave write and
Standard mode at 100kbits/s
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
terminate the transfer. The write or read block both begins with the master sending a slave
address and a write condition (0xD2) or a read condition (0xD3).
Following the acknowledge of this address byte, in
Write Mode:
the
Command Byte
and
Byte
Count Byte
must be sent by the master
but ignored by the slave, in
Read Mode:
the
Byte
Count Byte
will be
read by the master
then all other
Data Byte
.
Byte Count Byte
default at
power-up is = (0x09).
I2C CONTROL REGISTERS
1. BYTE 6: Outputs Register
(1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7
48
1
SEL_DDR ( I2C is ready only, value is set through pin48 )
Bit 6
-
0
Enhanced SDRAM Drive. 1 = Enhanced 25%
Bit 5
-
0
Enhanced DDR Drive. 1 = Enhanced 25%
Bit 4
-
0
Reserved
Bit 3
45, 44
1
DDR11T, DDR11C
Bit 2
43, 42
1
DDR10T, DDR10C
Bit 1
39, 38
1
DDR9T, DDR9C
Bit 0
34, 33
1
DDR8T, DDR8C
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PLL103-02XC-R | 制造商:PLL 制造商全稱:PLL 功能描述:DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS |
| PLL103-02XI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS |
| PLL103-02XM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS |
| PLL103-03 | 制造商:PLL 制造商全稱:PLL 功能描述:DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS |
| PLL103-03XC | 制造商:PLL 制造商全稱:PLL 功能描述:DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS |
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